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sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 1 version 1.6 sn8f 22 8 0 series users manual sn8 f 22 88 SN8F2283 s s o o n n i i x x 8 8 - - b b i i t t m m i i c c r r o o - - c c o o n n t t r r o o l l l l e e r r sonix reserves the right to make change without further notice to any products herein to improve reliability, function or des ign. sonix does no t assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. sonix products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the f ailure of the sonix product could create a situation where personal injury or death m ay occur. should buyer purchase or use sonix products for any such unintended or unauthorized application. buyer shall indemnify and hold sonix and its officers, employees, subsidiaries, affiliates and dist ributors harmless against all claims, cost, damage s, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manu facture of the part.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 2 version 1.6 amendment history version date description ver 1.0 200 9 / 0 3 / 0 6 1. first version is released . ver 1.1 2009/08/11 1. remove adc external high reference voltage source from p40. 2. modify wakeup time s description . 3. modify uart baud rate pre - sca lar s description . 4. modify sio s transfer rate select bit. ver 1.2 2009/10/ 20 1. add SN8F2283 related information. 2. modify the minimum of low voltage reset level middle in 17.2 electronical characteristic . ver 1.3 2009/11/0 5 1. update the package information of qfn 24pin in 19.3 qfn 24 pin . ver 1.4 2009/ 11 / 16 1. update low voltage reset level in 17.2 electronical characteris tic . 2. remove lvd_l selection in 2.1.2 code option table . 3. replace ext_osc with high_clk in 2.1.2 code option table . 4. add information of sn8ice 2k plus ii and ev - kit v3.0. ver 1. 5 2010/01/05 1. update the package information d2 of qfn 48pin in 19.2 qfn 48 pin . ver 1.6 2010/09/09 1. update the package information d2 & e2 of qfn 48pin in 19.2 qfn 48 pin .
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 3 version 1.6 table of con tent amendment history ................................ ................................ ................................ .......................... 2 1 product overview ................................ ................................ ................................ ......................... 9 1.1 features ................................ ................................ ................................ ................................ .............. 9 1.2 system block diagram ................................ ................................ ................................ .............. 10 1.3 pin assignment ................................ ................................ ................................ ............................... 11 1.4 pin descriptions ................................ ................................ ................................ ............................. 12 1.5 pin circuit diagrams ................................ ................................ ................................ ................... 14 2 central processor un it (cpu) ................................ ................................ .............................. 15 2.1 memory map ................................ ................................ ................................ ................................ ..... 15 2.1.1 program memory (rom) ................................ ................................ ................................ ........ 15 2.1.1.1 reset vector (0000h) ................................ ................................ ................................ ...... 16 2.1.1.2 interrupt vector (0008h) ................................ ................................ ............................. 17 2.1.1.3 look - up table description ................................ ................................ ........................ 19 2.1.1.4 jump table description ................................ ................................ ............................... 21 2.1.1.5 checksum calculation ................................ ................................ ............................... 23 2.1.2 code option table ................................ ................................ ................................ .................. 24 2.1.3 data me mory (ram) ................................ ................................ ................................ .................. 25 2.1.4 system register ................................ ................................ ................................ ........................ 27 2.1.4.1 system register table ................................ ................................ ................................ 27 2.1.4.2 system register description ................................ ................................ ................... 27 2.1.4.3 bit definition of system register ................................ ................................ ........... 28 2.1.4.4 accumulator ................................ ................................ ................................ ................... 31 2.1.4.5 program flag ................................ ................................ ................................ ................... 32 2.1.4.6 program counter ................................ ................................ ................................ ........... 33 2.1.4.7 y, z registers ................................ ................................ ................................ ..................... 36 2.1.4.8 r registers ................................ ................................ ................................ ......................... 37 2.2 addressing mode ................................ ................................ ................................ ........................... 38 2.2.1 immediate ad dressing mode ................................ ................................ .............................. 38 2.2.2 directly addressing mode ................................ ................................ ................................ . 38 2.2.3 indirectly addressing mode ................................ ................................ ............................. 38 2.3 stack operation ................................ ................................ ................................ ............................ 39 2.3.1 overview ................................ ................................ ................................ ................................ ..... 39 2.3.2 stack registers ................................ ................................ ................................ ........................ 40 2.3.3 stack operation example ................................ ................................ ................................ .... 41 3 reset ................................ ................................ ................................ ................................ ..................... 42
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 4 version 1.6 3.1 overview ................................ ................................ ................................ ................................ ........... 42 3.2 power on reset ................................ ................................ ................................ ............................... 44 3.3 watchdog reset ................................ ................................ ................................ ............................ 44 3.4 brown out reset ................................ ................................ ................................ ........................... 45 3.4.1 brown out description ................................ ................................ ................................ ........ 45 3.4.2 the system operating voltage decsription ................................ ............................... 46 3.4.3 brown out reset i mprovement ................................ ................................ ......................... 47 3.5 external reset ................................ ................................ ................................ .............................. 48 3.6 external reset circuit ................................ ................................ ................................ ............. 48 3.6.1 simply rc reset circuit ................................ ................................ ................................ .................. 48 3.6.2 diode & rc reset circuit ................................ ................................ ................................ ............... 49 3.6.3 zener diode reset circuit ................................ ................................ ................................ ............... 49 3.6.4 voltage bias reset circuit ................................ ................................ ................................ ............... 50 3.6.5 external reset ic ................................ ................................ ................................ ............................. 50 4 system clock ................................ ................................ ................................ ................................ .. 51 4.1 overview ................................ ................................ ................................ ................................ ........... 51 4.2 clock block diagram ................................ ................................ ................................ ................. 51 4.3 oscm register ................................ ................................ ................................ ................................ . 52 4.4 system high clock ................................ ................................ ................................ ....................... 53 4.4.1 external high clock ................................ ................................ ................................ ............. 53 4.4.1.1 crystal/c eramic ................................ ................................ ................................ ............. 54 4.4.1.2 external clock signal ................................ ................................ ............................... 55 4.5 system low clock ................................ ................................ ................................ ........................ 56 4.5.1 system clock measurement ................................ ................................ ............................... 57 5 system operation mod e ................................ ................................ ................................ ........... 58 5.1 overview ................................ ................................ ................................ ................................ ........... 58 5.2 system mode switching example ................................ ................................ ......................... 59 5.3 wakeup ................................ ................................ ................................ ................................ ............... 61 5.3.1 overview ................................ ................................ ................................ ................................ ..... 61 5.3.2 wakeup time ................................ ................................ ................................ ............................... 61 6 interrupt ................................ ................................ ................................ ................................ ........... 62 6.1 overview ................................ ................................ ................................ ................................ ........... 62 6.2 inten interrupt enable register ................................ ................................ ......................... 63 6.3 intrq interrupt request register ................................ ................................ ....................... 65 6.4 gie global interrupt operation ................................ ................................ .......................... 66 6.5 push, pop routine ................................ ................................ ................................ ........................... 66 6.6 int0 (p0.0) & int1 (p0.1) interrupt operation ................................ ................................ ....... 68 6.7 t0 interrupt operation ................................ ................................ ................................ .............. 70
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 5 version 1.6 6.8 t1 interrupt operation ................................ ................................ ................................ .............. 71 6.9 tc0 interrupt operation ................................ ................................ ................................ ........... 72 6.10 tc1 interrupt operation ................................ ................................ ................................ ......... 73 6.11 tc2 interrupt operation ................................ ................................ ................................ ......... 74 6.12 usb interrupt operat ion ................................ ................................ ................................ ........ 75 6.13 wakeup interrupt operation ................................ ................................ ............................... 76 6.14 sio interrupt operation ................................ ................................ ................................ .......... 77 6.15 multi - interrupt operation ................................ ................................ ................................ ... 78 7 i/o port ................................ ................................ ................................ ................................ ................ 79 7.1 i/o port mode ................................ ................................ ................................ ................................ ... 79 7.2 i/o pull up register ................................ ................................ ................................ ...................... 80 7.3 i/o open - drain register ................................ ................................ ................................ .............. 81 7.4 i/o port data register ................................ ................................ ................................ ................ 82 7.5 i/o port1 wakeup control register ................................ ................................ ..................... 83 8 timers ................................ ................................ ................................ ................................ .................. 84 8.1 watchdog timer ................................ ................................ ................................ ............................ 84 8.2 timer 0 (t0) ................................ ................................ ................................ ................................ ......... 86 8.2.1 overview ................................ ................................ ................................ ................................ ..... 86 8.2.2 t0m mode register ................................ ................................ ................................ .................. 86 8.2.3 t0c counting register ................................ ................................ ................................ .......... 87 8.2.4 t0 timer operation sequence ................................ ................................ ............................ 88 8.3 time r t1 (t1) ................................ ................................ ................................ ................................ ....... 89 8.3.1 overview ................................ ................................ ................................ ................................ ..... 89 8.3.2 t1m mode register ................................ ................................ ................................ .................. 89 8.3.3 t1c counting register ................................ ................................ ................................ .......... 90 8.3.4 t1 timer operation sequence ................................ ................................ ............................ 90 8.4 timer/counter 0 (tc0~tc2) ................................ ................................ ................................ ......... 92 8.4.1 overview ................................ ................................ ................................ ................................ ..... 92 8.4.2 tcnm mode register ................................ ................................ ................................ ............... 93 8.4.3 tcnc counting register ................................ ................................ ................................ ....... 95 8.4.4 tcnr auto - load register ................................ ................................ ................................ ..... 96 8.4.5 tcn clock frequency output (buzzer) ................................ ................................ ......... 97 8.4.6 tcn timer operation sequence ................................ ................................ ......................... 98 8.5 pwm n mode ................................ ................................ ................................ ................................ ........ 99 8.5.1 overview ................................ ................................ ................................ ................................ ..... 99 8.5.2 tcnirq and pwm duty ................................ ................................ ................................ ................ 100 8.5.3 pwm duty with tcnr changing ................................ ................................ ................................ .. 101 8.5.4 pwm program example ................................ ................................ ................................ ....... 102
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 6 version 1.6 9 universal serial bus (usb) ................................ ................................ ................................ ..... 103 9.1 overview ................................ ................................ ................................ ................................ ......... 103 9.2 usb machine ................................ ................................ ................................ ................................ ... 103 9.3 usb interrupt ................................ ................................ ................................ ................................ 104 9.4 usb enumeration ................................ ................................ ................................ ......................... 104 9.5 usb registers ................................ ................................ ................................ ................................ 105 9.5.1 usb device address register ................................ ................................ ........................... 105 9.5.2 usb status register ................................ ................................ ................................ .............. 105 9.5.3 usb da ta count register ................................ ................................ ................................ ... 106 9.5.4 usb enable control register ................................ ................................ .......................... 106 9.5.5 usb endpoints ack handshaking flag register ................................ ................................ ..... 107 9.5.6 usb endpoints nak handshaking flag register ................................ ................................ ..... 107 9.5.7 usb endpoint 0 enable register ................................ ................................ ..................... 108 9.5.8 usb endpoint 1 enable register ................................ ................................ ..................... 108 9.5.9 usb endpoint 2 enable register ................................ ................................ ..................... 109 9.5.10 usb endpoint 3 enabl e register ................................ ................................ ................... 110 9.5.11 usb endpoint 4 enable register ................................ ................................ ................... 111 9.5.12 usb endpoint fifo address setting register ................................ ......................... 111 9.5.13 usb data pointer register ................................ ................................ .............................. 112 9.5.14 usb data read/write register ................................ ................................ ........................ 112 9.5. 15 upid register ................................ ................................ ................................ ........................ 112 9.5.16 endpoint toggle bit control register ................................ ................................ .... 113 10 universal asynchrono us receiver/transmit ter (uart) .............................. 114 10.1 overview ................................ ................................ ................................ ................................ ....... 114 10.2 uart operation ................................ ................................ ................................ .......................... 114 10.3 uart transmitter c ontrol register ................................ ................................ ............. 117 10.4 uart receiver control register ................................ ................................ ...................... 118 10.5 uart baud rate control register ................................ ................................ ................... 119 10.6 uart data buffer ................................ ................................ ................................ ...................... 120 11 serial input/output transceiver ................................ ................................ ................ 121 11.1 overview ................................ ................................ ................................ ................................ ....... 121 11.2 siom mode register ................................ ................................ ................................ .................. 124 11.3 siob data buffer ................................ ................................ ................................ ....................... 125 11.4 sior register description ................................ ................................ ................................ ..... 125 12 8 channel analog to digital converter ................................ ............................... 127 12.1 overview ................................ ................................ ................................ ................................ ....... 127 12.2 adm register ................................ ................................ ................................ ............................... 128
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 7 version 1.6 12.3 adr registers ................................ ................................ ................................ .............................. 128 12.4 adb registers ................................ ................................ ................................ .............................. 129 12.5 p4con registers ................................ ................................ ................................ .......................... 130 12.6 adc converting time ................................ ................................ ................................ ............... 130 12.7 adc contorl notice ................................ ................................ ................................ ................. 131 12.7.1 adc signal ................................ ................................ ................................ ............................... 131 12.7.2 adc program ................................ ................................ ................................ ......................... 13 1 12.8 adc circuit ................................ ................................ ................................ ................................ ... 132 13 main series port (ms p) ................................ ................................ ................................ .......... 133 13.1 overview ................................ ................................ ................................ ................................ ....... 133 13.2 msp status register ................................ ................................ ................................ ................. 133 13.3 msp mode register 1 ................................ ................................ ................................ ................. 134 13.4 msp mode register 2 ................................ ................................ ................................ ................. 135 13.5 msp buffer r egister ................................ ................................ ................................ ................. 136 13.6 msp address register ................................ ................................ ................................ ............. 136 13.7 s lave m ode o peration ................................ ................................ ................................ .................... 137 13.7.1 addressing ................................ ................................ ................................ ................................ ... 137 13.7.2 slave receiving ................................ ................................ ................................ ............................ 137 13.7.3 slave transmission ................................ ................................ ................................ ...................... 138 13.7.4 general call address ................................ ................................ ................................ .................. 139 13.7.5 slave wake up ................................ ................................ ................................ .............................. 139 13.8 m aster m ode o peration ................................ ................................ ................................ ................. 141 13.8.1 master mode support ................................ ................................ ................................ .................. 141 13.8.2 msp rate generator (mrg) ................................ ................................ ................................ ....... 141 13.8.3 msp mas ter mode start condition ................................ ................................ .......................... 142 13.8.4 msp master mode repeat start condition ................................ ................................ .............. 142 13.8.5 acknowledge sequence timing ................................ ................................ ................................ ... 143 13.8.6 msp master mode stop condition timing ................................ ................................ ............... 143 13.8.7 clock arbitration ................................ ................................ ................................ ......................... 144 13.8.8 master mode transmission ................................ ................................ ................................ ......... 145 13.8.9 master mode receiving ................................ ................................ ................................ ............... 146 14 flash ................................ ................................ ................................ ................................ ............... 147 14.1 overview ................................ ................................ ................................ ................................ ....... 147 14.2 flash programming/erase control register ................................ ........................... 148 14.3 programming/erase address registe r ................................ ................................ ......... 148 14.4 programming/erase data register ................................ ................................ ................ 150 14.4.1 f lash i n - system - programming mapping address ................................ ............................ 150 15 instruction table ................................ ................................ ................................ ................. 151
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 8 version 1.6 16 development tool ................................ ................................ ................................ ................ 152 16.1 ice (i n c ircuit e mulation ) ................................ ................................ ................................ ......... 152 16.2 sn8f2280 ev - k it ................................ ................................ ................................ .......................... 154 16.3 sn8f2280 t ransition b oard ................................ ................................ ................................ ...... 156 17 elect rical characteristic ................................ ................................ ............................ 157 17.1 absolute maximum rating ................................ ................................ .............................. 157 17.2 electrical characteristic ................................ ................................ ............................. 157 18 flash rom programmin g pin ................................ ................................ ........................... 159 19 package information ................................ ................................ ................................ ......... 160 19.1 lqfp 48 pin ................................ ................................ ................................ ................................ ....... 160 19.2 qfn 48 pin ................................ ................................ ................................ ................................ ........ 161 19.3 qfn 24 pin ................................ ................................ ................................ ................................ ........ 162 20 marking definition ................................ ................................ ................................ ............... 163 20.1 introduction ................................ ................................ ................................ .......................... 163 20.2 marking indetification system ................................ ................................ .................... 163 20.3 marking exampl e ................................ ................................ ................................ ................. 164 20.4 datecode system ................................ ................................ ................................ .................. 164
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 9 version 1.6 1 product overview 1.1 features ? features selection table chip rom ram timer sio uart pwm a/d usb msp wakeup pin. i/o pin package t0 t1 tc0 tc1 tc2 sn8f2288 12k*16 512*8 v v v v v v v v 12bit v v 16 38 lqfp /qfn SN8F2283 12k*16 512*8 v v v v v x v x x v x 10 12 qfn ? memory configuration ? 15 interrupt sources. flash rom size : 12k x 16 bits , including in system programming function. 20000 erase/write cycles. 11 internal interrupts: t0, t1, tc0, tc1, tc2, usb, sio, i/o pin wakeup, uart, msp , a/d ram size : 512 x 8 bits. 4 external interrupts: int0, int1, p0, p1 ? 8 levels stack buff er ? one sio function for data transfer (serial peripheral interface) ? i/o pin configuration bi - directional: p0, p1, p2, p4, p5 ? one 8 bits timer counter (t0 ). wakeup: p0/p1 level change. p0, p1, p2, p4, p5 with pull up function ? three 8 bits timer counter (tc0, tc1, tc2) external interrupt: p0, p1 (level change) tc0, tc1, tc2. each has 8 bit pwm function (duty/cycle programmable). p0.5, p0.6, p1.0, p1.1 with open drain function. ? one 16 bit s timer counter (t 1 ). ? full speed us b 2.0 conforms to usb specification, version 2.0 ? one channel uart function 3.3v regulated output/driving 6 0ma internal d+ 1.5k ohm pull - up resistor. ? one channel msp function. 1 control endpoint . 2 bi - directional int endpoints ? 8 channe l 12 bit a/d function. 1 bi - directional int/bulk in endpoint. 1 bi - directional int/bulk out endpoints. ? two system clocks. programmable ep1~ep4 fifo depth external high clock: crystal type 6mhz/12mhz/16mhz internal low clock: rc type 12khz ? powerful instructions one clocks per instruction cycle (1t) ? four operating modes. most of instructions are one cycle only. normal mode: both high and low clock active all rom area jmp instruction. slow mode: low clock only all rom area call address instruction. sleep mode: both high and low clock stop all rom area lookup table function (movc) green mode: periodical wakeup by timer ? in - system re - programmability ? package allows easy firmware update lqfp48 /qfn48 /qfn24 ? on c hip watchdog timer.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 10 version 1.6 1.2 system block diagram i n t e r r u p t c o n t r o l 6 m h z / 1 2 m h z / 1 6 m h z e x t e r n a l o s c i l l a t o r a c c i n t e r n a l l o w r c t i m i n g g e n e r a t o r r a m s y s t e m r e g i s t e r s l v d w a t c h d o g t i m e r t i m e r & c o u n t e r a l u p c f l a g s i r f l a s h m e m o r y f u l l s p e e d u s b s i e 3 . 3 v r e g u l a t o r v r e g 3 3 d + d - p l l p 0 p 1 p 2 p 4 2 . 5 v r e g u l a t o r p 5 s i o p w m a / d u a r t m s p
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 11 version 1.6 1.3 pin assignment sn8f2288f (lqfp 48 pins) sn8f2288j (qfn 48 pins) p1.3 p1.4 p1.5 p1.6 p 1.7 p5.5/pwm2 p5.4/pwm1 p5.3/pwm0 p5.2 p5.1 p5.0 p2.7 48 47 46 45 44 43 42 41 40 39 38 37 p1.2 1 36 p2.6 p1.1/sda 2 35 p2.5 p1.0/scl 3 34 p2.4 p0.0/int0 4 33 p2.3 p0.1/int1 5 32 p2.2 /sdi p0.2 6 sn8f2288f /sn8f2288j 31 p2.1/sdo vdd 7 30 p2.0 /sck p4.0/ain0 8 29 vdd p4.1/ain1 9 28 vreg 33 p4.2/ain2 10 27 d - p4.3/ain3 11 26 d+ p4.4/ain4 12 25 vss 13 14 15 16 17 18 19 20 21 22 23 24 p4.5/ain5 p4. 6 /ain6 p4. 7 /a in7 vss p0.3 p0.4 p0.5/urx p0.6/utx p0.7/rst xin xout vreg25 sn8 f 2 283j ( qfn 24 pins ) p2.6 vdd vreg33 dn dp vss 24 23 22 21 20 19 p2.7 1 18 vreg25 vss 2 17 xout p 1.6 3 SN8F2283j 16 xin p 1.5 4 15 p 0.6/utx p1.4 5 14 p0.5/urx p 1.3 6 13 vss 7 8 9 10 11 12 p1.2 p0.0/int0 p0.1/int1 p0.2 vdd vss
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 12 version 1.6 1.4 pin descriptions pin name type description vdd, vss p power supply input pins for digital circuit. p0.0/int0 i/o p0.0: port 0.0 bi - direction pin. schmitt trigger structure and built - in pull - up resisters as input mode. built wakeup function. int0: external interrupt 0 input pin. p0.1/int1 i/o p0 .1: port 0.1 bi - direction pin. schmitt trigger structure and built - in pull - up resisters as input mode. built wakeup function. int1: external interrupt 1 input pin. p0[ 4 : 2 ] i/o p0: port 0 bi - direction pin. schmitt trigger structure and built - in pull - up re sisters as input mode. built wakeup function. p0.5/urx i/o p0.5: port 0 bi - direction pin schmitt trigger structure and built - in pull - up resistor as input mode. built wakeup function. uart function: urx pin open drain function by control register p1oc p0. 6/utx i/o p0.6: port 0 bi - direction pin schmitt trigger structure and built - in pull - up resistor as input mode. built wakeup function. uart function: utx pin open drain function by control register p1oc p0.7/rst i/o rst is system external reset input pin u nder ext_rst mode, schmitt trigger structure, active Dlow, and normal stay to Dhigh. built wakeup function. p1. 0 /s cl i/o p1.0: port 1.0 bi - direction pin. schmitt trigger structure and built - in pull - up resisters as input mode. built wakeup function. open drain function by control register p1oc msp function: s cl function p1.1/s da i/o p1.1: port 1.1 bi - direction pin. schmitt trigger structure and built - in pull - up resisters as input mode. built wakeup function. open drain function by control register p1oc m sp function: s da function p1[7:2] i/o p1: port 1 bi - direction pin. schmitt trigger structure and built - in pull - up resisters as input mode. built wakeup function. p2.0/sck i/o p2.0: port 2.0 bi - direction pin. schmitt trigger structure and built - in pull - u p resisters as input mode. sck: sio output clock pin. p2.1/sdo i/o p2.1: port 2.1 bi - direction pin. schmitt trigger structure and built - in pull - up resisters as input mode. sdo: sio data output pin. p2.2/sdi i/o p2. 2 : port 2.2 bi - direction pin. schmitt tr igger structure and built - in pull - up resisters as input mode. sdi: sio data input pin. p2[5:3] i/o p2: port 2 bi - direction pin. schmitt trigger structure and built - in pull - up resisters as input mode. p4[7:0]/ain[7:0] i/o p4: port 4 bi - direction pin. buil t - in pull - up resisters as input mode. ain[7:0]: adc channel C 0~7 input. p5[2:0] i/o p5: port 5 bi - direction pin. schmitt trigger structure and built - in pull - up resisters as input mode. p5[5:3]/pwm2~pwm0 i/o p5: port 5 bi - direction pin. schmitt trigger s tructure and built - in pull - up resisters as input mode. pwm0, pwm1, pwm2: pwm function
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 13 version 1.6 xout i/o xout: oscillator output pin while external crystal enable. xin i/o xin: oscillator input pin while external oscillator enable (crystal and rc). vreg25 p 2.5v power pin. please connect 1uf capacitor to gnd. vreg33 p 3.3v power pin. please connect xuf capacitor to gnd. x=1~10. d+, d - i/o usb differential data line.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 14 version 1.6 1.5 pin circuit diagrams port 0, 1, 2 , 4, 5 structures: p ort 0. 7 structure: pull-up pin output latch pnur input bus pnm output bus pin ext. reset code option int. bus int. rst
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 15 version 1.6 2 central processor unit (cpu) 2.1 memory map 2.1.1 program memory (rom) ? 1 2 k words rom rom 0000h reset vector user reset vector jump to user start address 0001h general purpose area . . 0007h 0008h interrupt vector user interrupt vector 0009h general purpose area user program . . 000fh 0010h 0011h . . . . . end of user program 2f f 8 h reserved . . 2 f ffh
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 16 version 1.6 2.1.1.1 reset vector (0000h ) a one - word vector address area is used to execute system reset. ? power on reset (nt0=1, npd=0). ? watchdog reset (nt0=0, npd=0). ? external reset (nt0=1, npd=1). after power on reset, external reset or watchdog timer overflow reset, then the chip will res tart the program from address 0000h and all system registers will be set as default values. it is easy to know reset status from nt0, npd flags of pflag register. the following example shows the way to define the reset vector in the program memory. ? exampl e: defining reset vector org 0 ; 0000h jmp start ; jump to user program address. org 10h start: ; 0010h, the head of user program. endp ; end of program
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 17 version 1.6 2.1.1.2 interrupt vector (0008 h) a 1 - word vector address area is used to execute interrupt request. if any interrupt service executes, the program counter (pc) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt. users have to define t he interrupt vector. the following example shows the way to define the interrupt vector in the program memory. ? note : push, pop instructions save and load acc/pflag without (nt0, npd). push/pop buffer is a unique buffer and only one level. ? examp le: defining interrupt vector. the interrupt service routine is following org 8. .code org 0 ; 0000h jmp start ; jump to user program address. org 8 ; interrupt vector. push ; save acc and pflag register to buffers. po p ; load acc and pflag register from buffers. reti ; end of interrupt service routine
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 18 version 1.6 ? example: defini ng interrupt vector. the interrupt service routine is following user program. .code org 0 ; 0000h jmp start ; jump to user program address. org 8 ; interrupt vector. jmp my_irq ; 0008h, jump to interrupt service routine address. o rg 10h start: ; 0010h, the head of user program. my_irq: ;the head of interrupt service routine. push ; save acc and pflag register to buffers. pop ; load a cc and pflag register from buffers. reti ; end of interrupt service routine. ? note: it is easy to understand the rules of sonix program from demo programs given above. these points are as following: 1. the address 00 00h is a jmp instruction to make the program starts from the beginning. 2. the address 0008h is interrupt vector. 3. users program is a loop routine for main purpose application.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 19 version 1.6 2.1.1.3 look - up table description in the roms data lookup function, y r egister is pointed to middle byte address (bit 8~bit 15) and z register is pointed to low byte address (bit 0~bit 7) of rom. after movc instruction executed, the low - byte data will be stored in acc and high - byte data stored in r register. ? t example: to loo k up the rom data located Dtable1. t b0mov y, #table1$m ; to set lookup table1s middle address ; to set lookup table1s low address. ; increment the index address for next addres s. incms z ; z+1 jmp @f ; z is not overflow. incms y ; z overflow (ffh ? 00), ? y=y+1 nop ; ; t @@: t movc ; to lookup data, r = 51h, acc = 05h. ? t note : t the y register will not increase automatically when z register crosses boundary from 0xff to 0x00. therefore, user must take care such situation to avoid loop - up table errors. if z register overflows, y register must be added one. the following inc_yz m acro shows a simple method to process y and z registers automatically. ? t example: inc_yz macro. t inc_yz macro incms z ; z+1 jmp @f ; not overflow incms y ; y+1 nop ; not overflow @@: endm
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 20 version 1.6 ? t example: modify above example by Di nc_yz macro. t b0mov y, #table1$m ; to set lookup table1s middle address ; to set lookup table1s low address. inc_yz ; increment the index address for next address. ; t @@: t movc ; to lookup data, r = 51h, acc = 05h. up table is to add y or z index register by accumulator. please be careful if Dcarry happen. ? t example: increase y and z register by b0add/add instruction. t b0mov y, #table1$m ; to set lookup tables middle address. ; to set lookup tables low address. b0mov a, buf ; z = z + buf. b0add z, a b0bts1 fc ; che ck the carry flag. jmp getdata ; fc = 0 incms y ; fc = 1. y+1. nop getdata: ; movc ; to lookup data. if buf = 0, data is 0x0035 ; if buf = 1, data is 0x5105 ; if buf = 2, data is 0x2012
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 21 version 1.6 2.1.1.4 jump table description the jump table operation is one of multi - address jumping function. add low - byte program counter (pcl) and acc value to get one new pcl. if pcl is overflow after pcl+acc, pch adds one automatically. the new program counter (pc) points to a series jump instructions as a listing table. it is easy to make a multi - jump program depends on the value of the accumulator (a). ? t note: t pch only support pc up counting result and doesnt support pc down counting. when pcl is carry after pcl+acc, pch adds one automatically. if pcl borrow after pcl C acc, pch keeps value and not change. ? example: jump table. org 0x0100 ; the jump table is from the head of the rom boundary b0add pc l, a ; pcl = pcl + acc, pch + 1 when pcl overflow occurs . jmp a0point ; acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point sonix provides a macro for safe jump table function. this macro will check the rom boundary and move the jump table to the right position automatically. the side effect of this macro maybe wastes some rom size. ? t example: if Djump table crosses over rom boundary will cause errors. @jmp_a macro val if (($+1) !& 0xff00) !!= (($+(val)) !& 0xff00) jmp ($ | 0xff) org ($ | 0xff) endif add pcl, a endm ? note: val is the number of the jump table listing number.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 22 version 1.6 ? example: D@jmp_a application in sonix macro file called Dmacro3.h. b0mov a, buf0 ; Dbuf0 is from 0 to 4. if the jump table position is across a rom boundary (0x00ff~0x0100), the D@jmp_a macro will adjust the jump table routine begin from next r o m boundary (0x0100). ? example: D@jmp_a operation. ; before compiling program. rom address b0mov a, buf0 ; Dbuf0 is from 0 to 4. ; after compiling program. rom address b0mov a, buf0 ; Dbuf0 is from 0 to 4.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 23 version 1.6 2.1.1.5 checksum calculation the last rom addresses are reserved area. user should avoid these addresses (last address) when calculate the checksum value. ? example: the demo program shows how to calculated checksu m from 00h to the end of users code. mov a,#end_user_code$l b0mov end_addr1, a ; save low end address to end_addr1 mov a,#end_user_code$m b0mov end_addr2, a ; save middle end address to end_addr2 clr y ; set y to 00h clr z ; set z to 00h @@ : movc b0bset fc ; clear c flag add data1, a ; add a to data1 mov a, r adc data2, a ; add r to data2 jmp end_check ; check if the yz address = the end of code aaa: incms z ; z=z+1 jmp @b ; if z != 00h calculate to next address jmp y_add_1 ; if z = 00h increase y end_check: mov a, end_addr1 cmprs a, z ; check if z = low end address jmp aaa ; if not jump to checksum calculate mov a, end_addr2 cmprs a, y ; if yes, check if y = middle end address jmp aaa ; if not jump to checksum calculate jmp checksum_end ; if yes checksum calculated is done. y_add_1: incms y ; increase y nop jmp @b ; jump to checksum calculate checksum_end: end_user_code: ; label of program end
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 24 version 1.6 2.1.2 co de option table code option content function description high_clk 6m_x'tal 6mhz crystal /resonator for external oscillator. 12m_x'tal 12mhz crystal /resonator for external oscillator. 16m_x'tal 16mhz crystal /resonator for external oscillator. watch _dog always_on watchdog timer is always on enable even in power down and green mode. enable enable watchdog timer. watchdog timer stops in power down mode and green mode. disable disable watchdog function. fcpu fhosc/1 instruction cycle is 12 mhz cloc k. fhosc/2 instruction cycle is 6 mhz clock. fhosc/4 instruction cycle is 3 mhz clock. fhosc/8 instruction cycle is 1.5 mhz clock. reset_pin reset enable external reset pin. p0 7 enable p0. 7 i/o function. fs low flosc/2 slow mode clock = flosc/2 . flosc/4 slow mode clock = flosc/4 . rst_length no no external reset de - bounce time. 128*ilrc external reset de - bounce time = 128*ilrc. lvd lvd_ m low voltage detect 2.4 v . lvd_h low voltage detect 3.6v . security enable enable rom code security functio n. disable disable rom code security function.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 25 version 1.6 2.1.3 data memory (ram) ? 512 x 8 - bit ram address ram location bank 0 000h general purpose area bank 0 D D D D D system register 80h~ffh of bank 0 store system re gisters (128 bytes). D D D D D end of bank 0 area bank1 100h general purpose area bank1 D D D D D bank2 20 0h general purpose area bank2 D D D D D
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 26 version 1.6 ? 136 x 8 - bit ram for usb data fifo ? endpoint 0 support only control pipe C 8 byte. ? endpoint 1 to endpoint 4, support interrupt data transfer, bulk data transfer C configurable fifo depth by setting the usb fifo control register. 13 6 x 8 ram (fifo) 00h endpoint 0 ram (8 byte) ~ 07h 0 8 h endpoint 1 ram ( w byte) interrupt in/out endpoint 2 ram ( x byte) interrupt in/out endpoint 3 ram (y byte) interrupt in/out bulk in/out endpoint 4 ram (z byte) interrupt in/out bulk in/out
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 27 version 1.6 2.1.4 system register 2.1.4.1 system register table 0 1 2 3 4 5 6 7 8 9 a b c d e f 8 - - r z y - pflag rbank tc0m tc0c tc0r tc1m tc1c tc1r tc2m tc2c 9 tc2r uda ustat us ep0ou t_cnt usb_in t_en ep _ack ep _nak ue0r ue1r u e1r_c ue2r ue2r_c ue3r ue3r_c ue4r ue4r_c a ep2fif o_add r ep3fif o_add r ep4fif o_add r udp0 - udr0_ r udr0_ w upid utoggle urtx urrx urbrc urtxd 1 urtxd 2 urrxd 1 urrxd 2 b siom sior siob - - p0m adm adb adr p4con pecmd perom l perom h peram l peram cnt pedge c p1w p 1m p2m - p4m p5m intrq1 inten1 intrq inten oscm - wdtr - pcl pch d p0 p1 p2 - p4 p5 - - t0m t0c t1m t1cl t1ch - - stkp e p0ur p1ur p2ur - p4ur p5ur - @yz - p1oc mspst at mspm1 mspm2 mspbu f mspad r - f stk7l stk7h stk6l stk6h stk5l stk5h stk4l stk4h stk3l stk3h stk2l stk2h stk1l stk1h stk0l stk0h 2.1.4.2 system register description r = working register and rom look - up data buffer. y, z = working, @yz and rom addressing register. pflag = rom page and special flag register. rbank = ram bank selection regi ster. uda = usb control register. ue x r = e px control registers. uexr_c = epx byte counter register. epxfifo_addr = epx fifo start address of usb fifo. udp0 = usb fifo address pointer. udr0 _r = usb fifo read data buffer by udp0 point to. udr0_w = usb fi fo write data buffer by udp0 point to. ep_nak = endpoint nak flag register. ep_ack = endpoint ack flag register. upid = usb bus control register. utoggle = usb endpoint toggle bit control register. usb_int_en = usb interrupt enable/disable control regist er. ustatus = usb status register. sior = sios clock reload buffer ep0out_cnt = usb endpoint 0 out token data byte counter pedge = p0.0, p0.1 edge direction register. siom = sio mode control register. inten = interrupt enable register. siob = sios da ta buffer. inten1 = interrupt1 enable register. pnm = port n input/output mode register. wdtr = watchdog timer clear register. intrq = interrupt request register. pch, pcl = program counter. intrq1 = interrupt1 request register. tnm = tn mode register. n = 0, 1, c0, c1, c2 oscm = oscillator mode register. tnr = tn register. n = c0, c1, c2 tc0r = tc0 auto - reload data buffer. stkp = stack pointer buffer. pn = port n data buffer. @yz = ram yz indirect addressing index pointer. tnc = timer counting regis ter. n = 0, 1, c0, c1, c2 stk0~stk7 = stack 0 ~ stack 7 buffer. pnur = port n pull - up resister control register. pecmd = isp command register. p1w = port 1 wakeup control register. peram = isp ram mapping address. perom = isp rom address. urtx = uart tx control regitster peramcnt = isp ram programming counter register. urbrc = uart baud rate register utrx = uart rx control register adm = a/d converter mode control register urxxdx = uart data buffer. mspstat = msp status register adb, adr = a/d conver ting data buffer. mspbuf = msp buffer. mspmx = msp mode register. mspadr = msp address.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 28 version 1.6 2.1.4.3 bit definition of system register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w remarks 082h rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 r/ w r 083h zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 r/w z 084h ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 r/w y 086h nt0 npd c dc z r/w pflag 087h rbnks1 rbnks0 r/w rbank 088h tc0enb tc0rate2 tc0rate1 tc0rate0 tc0cks aload0 tc0out p wm0out r/w tc0m 089h tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 r/w tc0c 08ah tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 r/w tc0r 08bh tc1enb tc1rate2 tc1rate1 tc1rate0 tc1cks aload 1 tc1out pwm1 out r/w tc1m 08ch tc1c7 tc1c6 tc1c5 tc1c4 tc1c3 tc1c2 tc1c1 tc1c0 r/w tc1c 08dh tc1r7 tc1r6 tc1r5 tc1r4 tc1r3 tc1r2 tc1r1 tc1r0 r/w tc1r 08eh tc2enb tc2rate2 tc2rate1 tc2rate0 tc2cks aload2 tc2out pwm2out r/w tc2m 08fh tc2c7 tc2c6 tc2c5 tc2c4 tc2c3 tc2c2 tc2c1 tc2c0 r/w tc2c 090h tc2r7 tc2r6 tc2r5 t c2r4 tc2r3 tc2r2 tc2r1 tc2r0 r/w tc2r 091h ude uda6 uda5 uda4 uda3 uda2 uda1 uda0 r/w uda 092h crcerr pkterr sof bus_rst suspend ep0setup ep0in ep0out r/w ustatus 093h uep0oc 4 uep0oc3 uep0oc2 uep0oc1 uep0oc0 r/w ep0out_cnt 094h reg_en dp_pu_en sof_i nt _en ep 4 nak _int_en ep3nak _int_en ep2nak _int_en ep1nak _int_en r/w usb_int_en 095h ep 4 _ack ep3_ack ep2_ack ep1_ack r/w ep_ack 096h ep 4 _nak ep3_nak ep2_nak ep1_nak r/w ep_nak 097h ue0m1 ue0m0 ue0c3 ue0c2 ue0c1 ue0c0 r/w ue0r 098h ue1e ue1 m1 ue1m0 r/w ue1r 099h ue1c6 ue1c5 ue1c4 ue1c3 ue1c2 ue1c1 ue1c0 rw ue1r_c 09ah ue2e ue2m1 ue2m0 r/w ue2r 09bh ue2c6 ue2c5 ue2c4 ue2c3 ue2c2 ue2c1 ue2c0 rw ue2r_c 09ch ue3e ue3m1 ue3m0 r/w ue3r 09dh ue3c6 ue3c5 ue3c4 ue3c3 ue3c2 ue3c 1 ue3c0 rw ue3r_c 09eh ue4e ue4m1 ue4m0 r/w ue4r 09fh ue4c6 ue4c5 ue4c4 ue4c3 ue4c2 ue4c1 ue4c0 rw ue4r_c 0a0h ep2fifo7 ep2fifo6 ep2fifo5 ep2fifo4 ep2fifo3 ep2fifo2 ep2fifo1 ep2fifo0 r/w ep2fifo_addr 0a1h ep3fifo7 ep3fifo6 ep3fifo5 ep3fifo4 ep3fi fo3 ep3fifo2 ep3fifo1 ep3fifo0 r/w ep3fifo_addr 0a2h ep4fifo7 ep4fifo6 ep4fifo5 ep4fifo4 ep4fifo3 ep4fifo2 ep4fifo1 ep4fifo0 r/w ep4fifo_addr 0a3h udp07 udp06 udp05 udp04 udp03 udp02 udp01 udp00 r/w udp0 0a5h udr0_r7 udr0_r6 udr0_r5 udr0_r4 udr0_r3 udr0 _r2 udr0_r1 udr0_r0 r/w udr0_r 0a6h udr0_w7 udr0_w6 udr0_w5 udr0_w4 udr0_w3 udr0_w2 udr0_w1 udr0_w0 r/w udr0_w 0a7h ubde ddp ddn r/w upid 0a8h ep4_data 01 ep3_data 01 ep2_data 01 ep1_data 01 r/w utoggle 0a9h uclks utxen utxpen utxps utxm r/ w urtx 0aah urxen urxs1 urxs0 urxpen urxps urxpc urxm r/w urrx 0abh udiv4 udiv3 udiv2 udiv1 udiv0 upcs2 upcs1 upcs0 r/w urbrc
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 29 version 1.6 0ach utxd17 utxd16 utxd15 utxd14 utxd13 utxd12 utxd11 utxd10 r/w urtxd1 0adh utxd27 utxd26 utxd25 utxd24 utxd23 utxd22 utxd21 utxd20 r/w urtxd2 0aeh u r xd 1 7 u r xd 1 6 u r xd 1 5 u r xd 1 4 u r xd 1 3 u r xd 1 2 u r xd 1 1 u r xd 1 0 r urrxd1 0afh u r xd 2 7 u r xd 2 6 u r xd 2 5 u r xd 2 4 u r xd 2 3 u r xd 2 2 u r xd 2 1 u r xd 2 0 r urrxd2 0b0h senb start srate1 srate0 mlsb sckmd cpol cpha r/w siom 0b1h sior7 sior6 sior5 sior4 sior 3 sior2 sior1 sior0 w sior 0b2h siob7 siob6 siob5 siob4 siob3 siob2 siob1 siob0 r/w siob 0b5h p07m p06m p05m p04m p03m p02m p01m p00m r/w p0m 0b6h adenb ads eoc gchs chs3 chs2 chs1 chs0 r/w adm 0b7h adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 r/w adb 0b 8h adcks2 adcks1 adcks0 adlen adb3 adb2 adb1 adb0 rw adr 0b9h p4con7 p4con6 p4con5 p4con4 p4con3 p4con2 p4con1 p4con0 r/w p4con 0bah pecmd7 pecmd6 pecmd5 pecmd4 pecmd3 pecmd2 pecmd1 pecmd0 w pecmd 0bbh peroml7 peroml6 peroml5 peroml4 peroml3 peroml2 per oml1 peroml0 r/w peroml 0bch per o mh7 per o mh6 per o mh5 per o mh4 per o mh3 per o mh2 per o mh1 per o mh0 r/w per o mh 0bdh peraml7 peraml6 peraml5 peraml4 peraml3 peraml2 peraml1 peraml0 r/w peraml 0beh peramcnt 4 peramcnt 3 peramcnt 2 peramcnt 1 peramcnt 0 peraml 9 peram l8 r/w peramcnt 0bfh p01g1 p01g0 p00g1 p00g0 r/w pedge 0c0h p17w p16w p15w p14w p13w p12w p11w p10w r/w p1w 0c1h p17m p16m p15m p14m p13m p12m p11m p10m r/w p1m 0c2h p27m p26m p25m p24m p23m p22m p21m p20m r/w p2m 0c4h p47m p46m p45m p44m p43m p42 m p41m p40m r/w p4 m 0c5h p55m p54m p53m p52m p51m p50m r/w p5m 0c6h p1irq p0irq mspirq utrxirq uttxirq t2cirq tc1irq tc0irq r/w intrq1 0c7h p1ien p0ien m s pien utrxien uttxien tc2ien tc1ien tc0ien r/w inten1 0c8h adcirq usbirq t1irq t0irq sioirq wakei rq p01irq p00irq r/w intrq 0c9h adcien usbien t1ien t0ien sioien wakeien p01ien p00ien r/w inten 0cah cpum1 cpum0 clkmd stphx r/w oscm 0cch wdtr7 wdtr6 wdtr5 wdtr4 wdtr3 wdtr2 wdtr1 wdtr0 w wdtr 0ceh pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 r/w pcl 0cfh pc13 pc12 pc11 pc10 pc9 pc8 r/w pch 0d0h p07 p06 p05 p04 p03 p02 p01 p00 r/w p0 0d1h p17 p16 p15 p14 p13 p12 p11 p10 r/w p1 0d2h p27 p26 p25 p24 p23 p22 p21 p10 r/w p2 0d4h p47 p46 p45 p44 p43 p42 p41 p40 r/w p4 0d5h p55 p54 p53 p52 p51 p50 r/w p5 0d8h t0enb t0rate2 t0rate1 t0rate0 r/w t0m 0d9h t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 r/w t0c 0dah t1enb t1rate2 t1rate1 t1rate0 r/w t1m 0dbh t1c7 t1c6 t1c5 t1c4 t1c3 t1c2 t1c1 t1c0 r/w t1cl 0dch t1c15 t1c14 t1c13 t1c12 t1c11 t1c10 t1c9 t1c8 r/w t1ch 0dfh gie stkpb2 stkpb1 stkpb0 r/w stkp 0e0h p07r p06r p05r p04r p03r p02r p01r p00r w p0ur 0e1h p17r p16r p15r p14r p13r p12r p11r p10r w p1ur 0e2h p27r p26r p25r p24r p23r p22r p21r p20r w p2ur 0e4h p47r p46r p45r p44r p43r p42r p41r p40 r w p4ur 0e5h p55r p54r p53r p52r p51r p50r w p5ur 0e7h @yz7 @yz6 @yz5 @yz4 @yz3 @yz2 @yz1 @yz0 r/w @yz 0e9h p06oc p05oc p11oc p10oc r/w p1oc 0eah cke d _ a p s red _ wrt bf r mspstat 0ebh wcol mspov mspenb ckp slrxckp mspwk mspc r/w mspm1 0ech gcen ackstat ackdt acken rcen pen rsen sen r/w mspm2 0edh mspbuf7 mspbuf6 mspbuf5 mspbuf4 mspbuf3 mspbuf2 mspbuf1 mspbuf0 r/w mspbuf 0eeh mspadr7 mspadr6 mspadr5 mspadr4 mspadr3 mspadr2 mspadr1 mspadr0 r/w mspadr 0f0h s7pc7 s7pc6 s7pc5 s7pc4 s7pc3 s7pc2 s7pc1 s7pc0 r/w stk7l 0f1h s7pc13 s7pc12 s7pc11 s7pc10 s7pc9 s7pc8 r/w stk7h 0f2h s6pc7 s6pc6 s6pc5 s6pc4 s6pc3 s6pc2 s6pc1 s6pc0 r/w stk6l 0f3h s6pc13 s6pc12 s6pc11 s6pc10 s6pc9 s6pc8 r/w stk6h 0f4h s5pc7 s5pc6 s5pc5 s5pc4 s5pc3 s5pc2 s5pc1 s5pc0 r/w stk5l 0f5h s5pc13 s5pc12 s5pc11 s5pc10 s5pc9 s5pc8 r/w stk5h 0f6h s4pc7 s4pc6 s4pc5 s4pc4 s4pc3 s4pc2 s4pc1 s4pc0 r/w stk4l 0f7h s4pc13 s4pc12 s4pc11 s4pc10 s4pc9 s4pc8 r/w stk4h 0f8h s3pc7 s3pc6 s3pc5 s3pc4 s3pc3 s3pc2 s3pc1 s3pc0 r/w stk3l 0f9h s3pc13 s3pc12 s3pc11 s3pc10 s3pc9 s3pc8 r/w stk3h 0fah s2pc7 s2pc6 s2pc5 s2pc4 s2pc3 s2pc2 s2pc1 s2pc0 r/w stk2l
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 30 version 1.6 0fbh s2pc13 s2pc12 s2pc11 s2pc10 s2pc9 s2pc8 r/w stk2h 0fch s1pc7 s1pc6 s1pc5 s1pc4 s1pc3 s1pc2 s1pc1 s1pc0 r/w stk1l 0fdh s1pc1 3 s1pc12 s1pc11 s1pc10 s1pc9 s1pc8 r/w stk1h 0feh s0pc7 s0pc6 s0pc5 s0pc4 s0pc3 s0pc2 s0pc1 s0pc0 r/w stk0l 0ffh s0pc13 s0pc12 s0pc11 s0pc10 s0pc9 s0pc8 r/w stk0h ? note: 1. to avoid system error, please be sure to put all the 0 and 1 as it indicat es in the above table t . 2. all of register names had been declared in sn8asm assembler. 3. one - bit name had been declared in sn8asm assembler with f prefix code. 4. b0bset, b0bclr, bset, bclr instructions are only available to the r/w registers. 5. for det ail description, please refer to the system register quick reference table .
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 31 version 1.6 2.1.4.4 accumulator the acc is an 8 - bit data register responsible for transferring or manipulating data between alu and data memory. if the result of operating is zero (z) or there is carry (c or dc) occurrence, then these flags will be set to pflag register. acc is not in data memory (ram), so acc cant be access by Db0mov instruction during the instant addressing mode. ? example: read and write acc value. ; read acc dat a and store in buf data memory. mov buf, a ; write a immediate data into acc. mov a, #0fh ; write acc data from buf data memory. mov a, buf ; or b0mov a, buf the system doesnt store acc and pflag value when interrupt executed. acc and pflag data must be saved to other data memories. Dpush, Dpop save and load acc, pflag data into buffers. ? example: protect acc and working registers. int_service: push ; save acc and pflag to buffers. pop ; l oad acc and pflag from buffers. reti ; exit interrupt service vector
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 32 version 1.6 2.1.4.5 program flag the pflag register contains the arithmetic status of alu operation; system reset status and lvd detecting status. nt0, npd bits indicate system rese t status including power on reset, lvd reset, reset by external pin active and watchdog reset. c, dc, z bits indicate the result status of alu operation. 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag nt0 npd - - - c dc z read/write r/w r/w - - - r/w r/w r/w after reset - - - - - 0 0 0 bit [7:6] nt0, npd: reset status flag. nt0 npd reset status 0 0 watch - dog time out 0 1 reserved 1 0 reset by lvd 1 1 reset by external reset pin bit 2 c: carry flag 1 = addition with carry, subtract ion without borrowing, rotation with shifting out logic D1, comparison result 0. 0 = addition without carry, subtraction with borrowing signal, rotation with shifting out logic D0, comparison result < 0. bit 1 dc: decimal carry flag 1 = addition with carry from low nibble, subtraction without borrow from high nibble. 0 = addition without carry from low nibble, subtraction with borrow from high nibble. bit 0 z: zero flag 1 = the result of an arithmetic/logic/branch operation is zero. 0 = the result o f an arithmetic/logic/branch operation is not zero. ? note: refer to instruction set table for detailed information of c, dc and z flags.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 33 version 1.6 2.1.4.6 program counter the program counter (pc) is a 1 4 - bit binary counter separated into the high - byte 6 and the low - byte 8 bits. this counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. normally, the program counter is automatically incremented with each instruction during program execution. besides, it can be re placed with specific address by executing call or jmp instruction. when jmp or call instruction is executed, the destination address will be inserted to bit 0 ~ bit 1 3 . bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pc - - pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 after reset - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pch pcl ? one address skipping there are nine instructions (cmprs, incs, incms, decs, decms, bts0, bts1, b0bts0, b0bts1 ) with one address skipping function. if the result of these instructions is true, the pc will add 2 steps to skip next instruction. if the condition of bit test instruction is true, the pc will add 2 steps to skip next instruction. b0bts1 fc ; to skip , if carry_flag = 1 jmp c0step ; else jump to c0step. b0bts0 fz ; to skip, if zero flag = 0. jmp c1step ; else jump to c1step. if the acc is equal to the immediate data or memory, the pc will add 2 steps to skip next instruction. cmprs a, #12h ; to skip, if acc = 12h. jmp c0step ; else jump to c0step.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 34 version 1.6 if the destination increased by 1, which results overflow of 0xff t o 0x00, the pc will add 2 steps to skip next instruction. incs instruction: incs buf0 jmp c0step ; jump to c0step if acc is not zero. c0step: nop incms instruction: incms buf0 jmp c0step ; jump to c0step if buf0 is not zero. c0step: nop if the destination decreased by 1, which results underflow of 0x00 to 0xff, the pc will add 2 steps to skip next instruction. decs instruction: decs buf0 jmp c0step ; jump to c0step if acc is not zero. c0step: no p decms instruction: decms buf0 jmp c0step ; jump to c0step if buf0 is not zero. c0step: nop
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 35 version 1.6 ? multi - address jumping users can jump around the multi - address by either jmp instruction or add m, a instruction (m = pcl) to activate multi - address jumping function. program counter supports Dadd m,a , adc m,a and Db0add m,a instructions for carry to pch when pcl overflow automatically. for jump table or others applications, users can calculate pc value by the three instructions and d ont care pcl overflow problem. ? note: pch only support pc up counting result and doesnt support pc down counting. when pcl is carry after pcl+acc, pch adds one automatically. if pcl borrow after pcl C acc, pch keeps value and not change. ? example: if pc = 0323h (pch = 03h, pcl = 23h) ; pc = 0323h mov a, #28h b0mov pcl, a ; jump to address 0328h ; pc = 0328h mov a, #00h b0mov pcl, a ; jump to address 0300h ? example: if pc = 0323h (pch = 03h, pcl = 23h) ; pc = 0323 h b0add pcl, a ; pcl = pcl + acc, the pch cannot be changed. jmp a0point ; if acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 36 version 1.6 2.1.4.7 y, z registers the y and z registers are the 8 - bit buffers. there are three major functions of these registers. ? can be used as general working registers ? can be used as ram data pointers with @yz register ? can be used as rom data pointer with the movc ins truction for look - up table 084h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 y ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset - - - - - - - - 083h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 z zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset - - - - - - - - example: uses y, z register as the data pointer to access data in the ram address 025h of bank0. b0mov y, #00h ; to set r am bank 0 for y register b0mov z, #25h ; to set location 25h for z register b0mov a, @yz ; to read a data into acc example: uses the y, z register as data pointer to clear the ram data. b0mov y, #0 ; y = 0, bank 0 b0mov z, #07fh ; z = 7fh, the last address of the data memory area clr_yz_buf: clr @yz ; clear @yz to be zero decms z ; z C
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 37 version 1.6 2.1.4.8 r registers r register is an 8 - bit buffer. there are two major functions of the register. ? can be used as working register ? for store high - byte data of look - up table (movc instruction executed, the high - byte data of specified rom add ress will be stored in r register and the low - byte data will be stored in acc). 082h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset - - - - - - - - ? note: please refer to the look - up table description about r register look - up table application.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 38 version 1.6 2.2 addressing mode 2.2.1 immediate addressing mode the immediate addressing mode uses an immediate data to set up the location in acc or specifi c ram. ? example: move the immediate data 12h to acc. mov a, #12h ; to set an immediate data 12h into acc. ? example: move the immediate data 12h to r register. b0mov r, #12h ; to set an immediate data 12h into r register. ? note: in immediate addres sing mode application, the specific ram must be 0x80~0x87 working register. 2.2.2 directly addressing mode the directly addressing mode moves the content of ram location in or out of acc. ? example: move 0x12 ram location data into acc. b0mov a, 12 h ; to get a content of ram location 0x12 of bank 0 and save in acc. ? example: move acc data into 0x12 ram location. b0mov 12h, a ; to get a content of acc and save in ram location 12h of bank 0. 2.2.3 indirectly addressing mode the indirectly add ressing mode is to access the memory by the data pointer registers (y/z). ? example: indirectly addressing mode with @yz register. b0mov y, #0 ; to clear y register to access ram bank 0. b0mov z, #12h ; to set an immediate data 12h into z register. b0 mov a, @yz ; use data pointer @yz reads a data from ram location ; 012h into acc.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 39 version 1.6 2.3 stack operation 2.3.1 overview the stack buffer has 8 - level. these buffers are designed to push and pop up program counters (pc) data when interrupt service r outine and Dcall instruction are executed. the stkp register is a pointer designed to point active level in order to push or pop up data from stack buffer. the stknh and stknl are the stack buffers to store program counter (pc) data. ret / reti call / interrupt stkp = 7 stkp = 6 stkp = 5 stkp = 4 stack level stk7h stk6h stk5h stk4h stack buffer high byte pch stkp stk7l stk6l stk5l stk4l stack buffer low byte pcl stkp stkp - 1 stkp + 1 stkp = 3 stkp = 2 stkp = 1 stkp = 0 stk3l stk2l stk1l stk0l stk3h stk2h stk1h stk0h
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 40 version 1.6 2.3.2 stack registers the stack pointer (stkp) is a 3 - bit register to store the address used to access the stack buffer, 1 4 - bit data memory (stknh and stknl) set aside for temporary storage of stack addresses. the two stack operations are writing to the top of the stack (push) and reading from the top of stack (pop). push operation decrements the stkp and the pop operation increments each time. that makes the stkp always point to the top address of stack buffer and write the last program co unter value (pc) into the stack buffer. the program counter (pc) value is stored in the stack buffer before a call instruction executed or during interrupt service routine. stack operation is a lifo type (last in and first out). the stack pointer (stkp) and stack buffer (stknh and stknl) are located in the system register area bank 0. 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - - stkpb2 stkpb1 stkpb0 read/write r/w - - - - r/w r/w r/w after reset 0 - - - - 1 1 1 bit 7 gie: global interrupt control bit. 0 = disable. 1 = enable. please refer to the interrupt chapter. bit[2:0] stkpbn: stack pointer (n = 0 ~ 2) ? example: stack pointer (stkp) reset, we strongly recommended to clear the stack pointers in the beginning of th e program. mov a, #00000111b b0mov stkp, a 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknh - - snpc13 snpc12 snpc11 snpc10 snpc9 snpc8 read/write - - r/w r/w r/w r/w r/w r/w after reset - - 0 0 0 0 0 0 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknl snpc7 snpc6 snpc5 snpc4 snpc3 snpc2 snpc1 snpc0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 stkn = stknh , stknl (n = 7 ~ 0)
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 41 version 1.6 2.3.3 stack operation example the two kinds of stack - save operations refer to the stack pointer (stkp) and write the content of program counter (pc) to the stack buffer are call instruction and interrupt service. under each condition, the stkp decreases and points to the next available stack location. the st ack buffer stores the program counter about the op - code address. the stack - save operation is as the following table. stack level stkp register stack buffer description stkpb2 stkpb1 stkpb0 high byte low byte 0 1 1 1 free free - 1 1 1 0 stk0h stk0l - 2 1 0 1 stk1h stk1l - 3 1 0 0 stk2h stk2l - 4 0 1 1 stk3h stk3l - 5 0 1 0 stk4h stk4l - 6 0 0 1 stk5h stk5l - 7 0 0 0 stk6h stk6l - 8 1 1 1 stk7h stk7l - > 8 1 1 0 - - stack over, error there are stack - restore operations correspond to each push operation to restore the program counter (pc). the reti instruction uses for interrupt service routine. the ret instruction is for call instruction. when a pop operation occurs, the stkp is incremented and points to the next free stack location. the stack buffer restores the last program counter (pc) to the program counter registers. the stack - restore operation is as the following table. stack level stkp register stack buffer description stkpb2 stkpb1 stkpb0 high byte low byte 8 1 1 1 stk7h stk7l - 7 0 0 0 stk6h stk6l - 6 0 0 1 stk5h stk5l - 5 0 1 0 stk4h stk4l - 4 0 1 1 stk3h stk3l - 3 1 0 0 stk2h stk2l - 2 1 0 1 stk1h stk1l - 1 1 1 0 stk0h stk0l - 0 1 1 1 free free -
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 42 version 1.6 3 reset 3.1 overview the system would be reset in three conditions as fo llowing. ? power on reset ? watchdog reset ? brown out reset ? external reset (only supports external reset pin enable situation) when any reset condition occurs, all system registers keep initial status, program stops and program counter is cleared. after res et status released, the system boots up and program starts to execute from org 0. the nt0, npd flags indicate system reset status. the system can depend on nt0, npd status and go to different paths by program. 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag nt0 npd - - - c dc z read/write r/w r/w - - - r/w r/w r/w after reset - - - - - 0 0 0 bit [7:6] nt0, npd: reset status flag. nt0 npd condition description 0 0 watchdog reset watchdog timer overflow. 0 1 reserved - 1 0 power on reset and lvd reset. power voltage is lower than lvd detecting level. 1 1 external reset external reset pin detect low level status.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 43 version 1.6 finishing any reset sequence needs some time. the system provides complete procedures to make the power on reset successful . for different oscillator types, the reset time is different. that causes the vdd rise rate and start - up time of different oscillator is not fixed. rc type oscillators start - up time is very short, but the crystal type is longer. under client terminal app lication, users have to take care the power on reset time for the master terminal requirement. the reset timing diagram is as following. vdd vss vdd vss watchdog normal run watchdog stop system normal run system stop lvd detect level external reset low detect external reset high detect watchdog overflow watchdog reset delay time external reset delay time power on delay time power external reset watchdog reset system status
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 44 version 1.6 3.2 power on reset the power on reset depend no lvd operation for most power - up situa tions. the power supplying to system is a rising curve and needs some time to achieve the normal voltage. power on reset sequence is as following. ? power - up: system detects the power voltage up and waits for power stable. ? external reset (only external rese t pin enable): system checks external reset pin status. if external reset pin is not high level, the system keeps reset status and waits external reset pin released. ? system initialization: all system registers is set as initial conditions and system is rea dy. ? oscillator warm up: oscillator operation is successfully and supply to system clock. ? program executing: power on sequence is finished and program executes from org 0. 3.3 watchdog reset watchdog reset is a system protection. in normal condition, s ystem works well and clears watchdog timer by program. under error condition, system is in unknown situation and watchdog cant be clear by program before watchdog timer overflow. watchdog timer overflow occurs and the system is reset. after watchdog reset , the system restarts and returns normal mode. watchdog reset sequence is as following. ? watchdog timer status: system checks watchdog timer overflow status. if watchdog timer overflow occurs, the system is reset. ? system initialization: all system register s is set as initial conditions and system is ready. ? oscillator warm up: oscillator operation is successfully and supply to system clock. ? program executing: power on sequence is finished and program executes from org 0. watchdog timer application note i s as following. ? before clearing watchdog timer, check i/o status and check ram contents can improve system error. ? dont clear watchdog timer in interrupt vector and interrupt service routine. that can improve main routine fail. ? clearing watchdog timer pro gram is only at one part of the program. this way is the best structure to enhance the watchdog timer function. ? note: please refer to the watchdog timer about watchdog timer detail information.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 45 version 1.6 3.4 brown out reset 3.4.1 brown out descri ption the brown out reset is a power dropping condition. the power drops from normal voltage to low voltage by external factors (e.g. eft interference or external loading changed). the brown out reset would make the system not work well or executing progr am error. brown out reset diagram the power dropping might through the voltage range thats the system dead - band. the dead - band means the power range cant offer the system minimum operation power requirement. the above di agram is a typical brown out reset diagram. there is a serious noise under the vdd, and vdd voltage drops very deep. there is a dotted line to separate the system working area. the above area is the system work well area. the below area is the system work error area called dead - band. v1 doesnt touch the below area and not effect the system operation. but the v2 and v3 is under the below area and may induce the system error occurrence. let system under dead - band includes some conditions. dc application: the power source of dc application is usually using battery. when low battery condition and mcu drive any loading, the power drops and keeps in dead - band. under the situation, the power wont drop deeper and not touch the system reset voltage. that makes the system under dead - band. ac application: in ac power application, the dc power is regulated from ac power source. this kind of power usually couples with ac noise that makes the dc power dirty. or the external loading is very heavy, e.g. driving motor. the loading operating induces noise and overlaps with the dc power. vdd drops by the noise, and the system works under unstable power situation. the power on duration and power down duration are longer in ac application. the system power on sequence protects t he power on successful, but the power down situation is like dc low battery condition. when turn off the ac power, the vdd drops slowly and through the dead - band for a while. vdd vss v1 v2 v3 system work well area system work error area
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 46 version 1.6 3.4.2 the system operating voltage decsription to improve t he brown out reset needs to know the system minimum operating voltage which is depend on the system executing rate and power level. different system executing rates have different system minimum operating voltage. the electrical characteristic section show s the system voltage to executing rate relationship. normally the system operation voltage area is higher than the system reset voltage to vdd, and the reset voltage is decided by lvd detect level. the system minimum operatin g voltage rises when the system executing rate upper even higher than system reset voltage. the dead - band definition is the system minimum operating voltage above the system reset voltage. vdd (v) system rate (fcpu) system mini. operating voltage. system reset voltage. dead-band area normal operating area reset area
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 47 version 1.6 3.4.3 brown out reset improvement how to improve the brown rese t condition? there are some methods to improve brown out reset as following. ? lvd reset ? watchdog reset ? reduce the system executing rate ? external reset circuit. (zener diode reset circuit, voltage bias reset circuit, external reset ic) ? note: 1. the zener d iode reset circuit, voltage bias reset circuit and external reset ic can completely improve the brown out reset, dc low battery and ac slow power down conditions. 2. for ac power application and enhance eft performance, the system clock is 4mhz/4 (1 mips ) and use external reset ( zener diode reset circuit, voltage bias reset circuit, external reset ic). the structure can improve noise effective and get good eft characteristic. lvd reset: the lvd (low voltage detector) is built - in sonix 8 - bit mcu to be brown out reset protection. when the vdd drops and is below lvd detect voltage, the lvd would be triggered, and the system is reset. the lvd detect level is different by each mcu. the lvd voltage level is a point of volta ge and not easy to cover all dead - band range. using lvd to improve brown out reset is depend on application requirement and environment. if the power variation is very deep, violent and trigger the lvd, the lvd can be the protection. if the power variation can touch the lvd detect level and make system work error, the lvd cant be the protection and need to other reset methods. more detail lvd information is in the electrical characteristic section. watchdog reset: the watchdog timer is a protection to ma ke sure the system executes well. normally the watchdog timer would be clear at one point of program. dont clear the watchdog timer in several addresses. the system executes normally and the watchdog wont reset system. when the system is under dead - band and the execution error, the watchdog timer cant be clear by program. the watchdog is continuously counting until overflow occurrence. the overflow signal of watchdog timer triggers the system to reset, and the system return to normal mode after reset seq uence. this method also can improve brown out reset condition and make sure the system to return normal mode. if the system reset by watchdog and the power is still in dead - band, the system reset sequence wont be successful and the system stays in reset status until the power return to normal range. reduce the system executing rate: if the system rate is fast and the dead - band exists, to reduce the system executing rate can improve the dead - band. the lower system rate is with lower minimum operating vol tage. select the power voltage thats no dead - band issue and find out the mapping system rate. adjust the system rate to the value and the system exits the dead - band issue. this way needs to modify whole program timing to fit the application requirement. external reset circuit: the external reset methods also can improve brown out reset and is the complete solution. there are three external reset circuits to improve brown out reset including Dzener diode reset circuit, Dvoltage bias reset circuit and Dex ternal reset ic. these three reset structures use external reset signal and control to make sure the mcu be reset under power dropping and under dead - band. the external reset information is described in the next section. vdd vss system normal run system stop lvd detect voltage power on delay time power system status power is below lvd detect voltage and system reset.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 48 version 1.6 3.5 external reset external res et function is controlled by Dreset_pin code option. set the code option as Dreset option to enable external reset function. external reset pin is schmitt trigger structure and low level active. the system is running when reset pin is high level voltage input. the reset pin receives the low voltage and the system is reset. the external reset operation actives in power on and normal running mode. during system power - up, the external reset pin must be high level input, or the system keeps in reset status. e xternal reset sequence is as following. ? external reset (only external reset pin enable): system checks external reset pin status. if external reset pin is not high level, the system keeps reset status and waits external reset pin released. ? system initiali zation: all system registers is set as initial conditions and system is ready. ? oscillator warm up: oscillator operation is successfully and supply to system clock. ? program executing: power on sequence is finished and program executes from org 0. the ex ternal reset can reset the system during power on duration, and good external reset circuit can protect the system to avoid working at unusual power condition, e.g. brown out reset in ac power application 3.6 external reset circuit 3. 6.1 simply rc rese t circuit this is the basic reset circuit, and only includes r1 and c1. the rc circuit operation makes a slow rising signal into reset pin as power up. the reset signal is slower than vdd power up timing, and system occurs a p ower on signal from the timing difference. ? note: the reset circuit is no any protection against unusual power or brown out reset. mcu vdd vss vcc gnd r s t r1 47k ohm c1 0.1uf r2 100 ohm
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 49 version 1.6 3. 6.2 diode & rc reset circuit this is the better reset circuit. the r1 and c1 circuit o peration is like the simply reset circuit to make a power on signal. the reset circuit has a simply protection against unusual power. the diode offers a power positive path to conduct higher power to vdd. it is can make reset pin voltage level to synchroni ze with vdd voltage. the structure can improve slight brown out reset condition. ? note: the r2 100 ohm resistor of simply reset circuit and diode & rc reset circuit is necessary to limit any current flowing into reset pin from external capacitor c in the event of reset pin breakdown due to electrostatic discharge (esd) or electrical over - stress (eos). 3. 6.3 zener diode reset circuit the zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition completely . use zener voltage to be the active level. when vdd voltage level is above Dvz + 0.7v, the c terminal of the pnp transistor outputs high voltage and mcu operates normally. when vdd is below Dvz + 0.7v, the c terminal of the pn p transistor outputs low voltage and mcu is in reset mode. decide the reset detect voltage by zener specification. select the right zener voltage to conform the application. mcu vdd vss vcc gnd r s t r1 47k ohm c1 0.1uf diode r2 100 ohm mcu vdd vss vcc gnd r s t r1 33k ohm r3 40k ohm r2 10k ohm vz q1 e c b
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 50 version 1.6 3. 6.4 voltage bias reset circuit the voltage bias r eset circuit is a low cost voltage detector and can improve brown out reset condition completely . the operating voltage is not accurate as zener diode reset circuit. use r1, r2 bias voltage to be the active level. when vdd voltage level is above or equal t o D0.7v x (r1 + r2) / r1, the c terminal of the pnp transistor outputs high voltage and mcu operates normally. when vdd is below D0.7v x (r1 + r2) / r1, the c terminal of the pnp transistor outputs low voltage and mcu is in reset mode. decide the reset detect voltage by r1, r2 resistances. select the right r1, r2 value to conform the application. in the circuit diagram condition, the mcus reset pin level varies with vdd voltage variation, and the differential voltage is 0.7v. if the vdd drops and the vo ltage lower than reset pin detect level, the system would be reset. if want to make the reset active earlier, set the r2 > r1 and the cap between vdd and c terminal voltage is larger than 0.7v. the external reset circuit is with a stable current through r1 and r2. for power consumption issue application, e.g. dc power system, the current must be considered to whole system power consumption. ? note: under unstable power condition as brown out reset, zener diode res e t circuit and voltage bias reset circuit can protects system no any error occurrence as power dropping. when power drops below the reset detect voltage, the system reset would be triggered, and then system executes reset sequence. that makes sure the system work well under unstable power situat ion. 3. 6.5 external reset ic the external reset circuit also use external reset ic to enhance mcu reset performance. this is a high cost and good effect solution. by different application and system requirement to select sui table reset ic. the reset circuit can improve all power variation . mcu vdd vss vcc gnd r s t r1 47k ohm r3 2k ohm r2 10k ohm q1 e c b mcu vdd vss vcc gnd r s t reset ic vdd vss rst bypass capacitor 0.1uf
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 51 version 1.6 4 system clock 4.1 overview the micro - controller is a dual clock system. there are high - speed clock and low - speed clock. the high - speed clock is generated from the external oscillator & on - chip pll circuit. the low - speed clock is generated from on - chip low - speed rc oscillator circuit (ilrc 12 khz ). both the high - speed clock and the low - speed clock can be system clock (fosc). the system clock in slow mode is divided by 2 or 4 to be the inst ruction cycle (fcpu). ? normal mode (high clock): fcpu = fhosc / n , n = 1 ~ 8 , select n by fcpu code option. ? slow mode (low clock): fcpu = flosc/ n, n = 2 or 4 , select n by code option. sonix provides a Dnoise filter controlled by code option. in high noisy situation, the noise filter can isolate noise outside and protect system works well. the minimum fcpu of high clock is limited at fhosc/4 when noise filter enable. 4.2 clock block diagram ? hosc: high_clk code optio n. ? fhosc: external high - speed clock. ? flosc: internal low - speed rc clock ( typical 12 khz ). ? fosc: system clock source. ? fcpu: instruction cycle. fhosc. fcpu = fhosc/1 ~ fhosc/8, noise filter disable. fcpu = fhosc/4, noise filter enable. flosc. fcpu = flosc/2 or flosc/4 cpum[1:0] xin xout stphx hosc fcpu code option fosc fosc clkmd fcpu
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 52 version 1.6 4.3 oscm register the oscm register is an oscillator control register. it controls oscillator status, system mode. 0cah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm - - - cpum1 cpum0 clkmd stphx - read/write - - - r/w r/w r/w r/w - after reset - - - 0 0 0 0 - bit[4:3] cpum[1:0]: cpu operating mode control bits. 00 = normal. 01 = sleep (power down) mode. 10 = green mode. 11 = reserved. bit 2 clkmd: system high/low clock mode control bit. 0 = normal (dual) mode. system clock is high clock. 1 = slow mode. system clock is internal low clock. bit 1 stphx: external high - speed oscillator control bit . 0 = external high - speed oscillator free run. 1 = external high - speed oscillator free run stop. internal low - speed rc oscillator is still running. ? example: stop high - speed oscillator and pll circuit. b0bset fstphx ; to stop external high - speed osci llator only. example: when entering the power down mode (sleep mode), both high - speed external oscillator , pll circuit and internal low - speed oscillator will be stopped. b0bset fcpum0 ; to stop external high - speed oscillator and internal low - spe ed ; oscillator called power down mode (sleep mode).
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 53 version 1.6 4.4 system high clock the system high clock is from the in circuit pll . user must select the external oscillator 6mhz x tal, 12mhz xtal or 16mhz xtal by the code option Dext_osc , and all the three clock source will input to the on - chip pll circuit. pll will output 12mhz to system clock (fosc). 4.4.1 external high clock external high clock includes three modules (crystal/ceramic and external clock signal). the start up time of crystal a nd ceramic oscillator is different. the oscillator start - up time decides reset time length.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 54 version 1.6 4.4.1.1 crystal/ceramic crystal/ceramic devices are driven by xin, xout pins. ? note: connect the crystal/ceramic and c as n ear as possible to the xin/xout/vss pins of micro - controller. m c u v c c g n d c 2 0 p f x i n x o u t v d d v s s c 2 0 p f c r y s t a l 1 . 6 k o h m
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 55 version 1.6 4. 4 .1.2 external clock signal selecting external clock signal input to be the input clock source is by the Dext_osc code option. the external clock signal is input from xin pin. xout pin is general purpose i/o pin. ? note: the gnd of external oscillator circuit must be as near as possible to vss pin of micro - controller. mcu vcc gnd vss vdd xin xout external clock input
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 56 version 1.6 4. 5 system low clock the system low clock source is the internal low - speed oscill ator built in the micro - controller. the low - speed oscillator uses rc type oscillator circuit. the frequency is affected by the voltage and temperature of the system. in common condition, the frequency of the rc oscillator is about 12k hz. the internal lo w rc supports watchdog clock source and system slow mode controlled by clkmd. ? flosc = internal low rc oscillator ( 12khz ) . ? slow mode fcpu = flosc / n. n = 2 or 4 set by code option . there are two conditions to stop internal low rc. one is power down mo de, and the other is green mode of 12 k mode and watchdog disable. if system is in 12 k mode and watchdog disable, only 12 k oscillator actives and system is under low power consumption. ? example: stop internal low - speed oscillator by power down mode. b 0bset fcpum0 ; to stop external high - speed oscillator and internal low - speed ; oscillator called power down mode (sleep mode). ? note: the internal low - speed clock cant be turned off individually. it is controlled by cpum0, cpum1 ( 1 2k, watchdog di sable) bits of oscm register.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 57 version 1.6 4. 5 .1 system clock measurement under design period, the users can measure system clock speed by software instruction cycle (fcpu). this way is useful in rc mode. example: fcpu instruction cycle of external oscillator . b0bset p0m.0 ; set p0.0 to be output mode for outputting fcpu toggle signal. @@: b0bset p0.0 ; output fcpu toggle signal in low - speed clock mode. b0bclr p0.0 ; measure the fcpu frequency by oscilloscope. jmp @b ? note: do not measur e the rc frequency directly from xin; the probe impendence will affect the rc frequency.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 58 version 1.6 5 system operation mode 5.1 overview the chip is featured with low power consumption by switching around four different modes as following. ? high - speed mode ? l ow - speed mode ? power - down mode (sleep mode) ? green mode system mode switching diagram operating mode description mode normal slow green power down (sleep) remark hosc running by stphx by stphx stop ilrc running running runn ing stop cpu instruction executing executing stop stop t0 timer *active *active *active inactive * active if t0enb=1 t 1 timer *active *active inactive inactive * active if t 1 enb=1 tc0 timer *active *active inactive inactive * active if tc0enb=1 tc1 timer *active *active inactive inactive * active if tc1enb=1 usb running inactive inactive inactive * active if usbe=1 watchdog timer by watch_dog code option by watch_dog code option by watch_dog code option by watch_dog code option refer to code option description internal interrupt all active all active t0 all inactive external interrupt all active all active all active all inactive wakeup source - - p0, p1, t0 , reset p0, p1, reset ? hosc: high clock ( fosc = 12mhz ) ? ilrc: internal low clock (1 2 k hz rc oscillator ) power down mode (sleep mode) slow mode green mode normal mode clkmd = 1 clkmd = 0 p0, p1 wake-up function active. usb bus. external reset circuit active. cpum1, cpum0 = 01. cpum1, cpum0 = 10. p0, p1 wake-up function active. t0 timer time out. usb bus. external reset circuit active. p0, p1 wake-up function active. t0 timer time out. usb bus. external reset circuit active.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 59 version 1.6 5.2 system mode switching example ? example: switch normal/slow mode to power down (sleep) mode. b0bset fcpum0 ; set cpum0 = 1. ? note: during the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode . ? example: switch normal mode to slow mode. b0bset fclkmd ;to set clkmd = 1, change the system into slow mode b0bset fstphx ;to stop external high - speed oscillator for power saving. ? example: switch slow mode to normal mode (the external high - speed oscillator is still running). b0bclr fclkmd ;to set clkmd = 0 example: switch slow mode to normal mode (the external high - speed oscillator stops). if external high clock stop and program want to switch back normal mode. it is necessary to del ay at least 10ms for external clock stable. b0bclr fstphx ; turn on the external high - speed oscillator. mov a, # 10 ; internal rc= 1 2khz (typical) will delay b0mov z, a @@: decms z ; 0. 33 ms x 30 ~ 10 ms for external clock stable jmp @b ; b0bclr fclkmd ; change the system back to the normal mode example: switch normal/slow mode to green mode. b0bset fcpum1 ; set cpum1 = 1. ? note: if t0 timer wakeup function is disabled in the green mode, only the wakeup pin and reset pin can wake up the system backs to the previous operation mode.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 60 version 1.6 example: switch normal/slow mode to green mode and enable t0 wake - up function. ; set t0 timer wakeup function. b0bclr ft0ien ; to disable t0 interrupt service b0bclr ft0enb ; to disable t0 tim er mov a,#20h ; b0mov t0m,a ; to set t0 clock = fcpu / 64 mov a,#74h b0mov t0c,a ; to set t0c initial value = 74h (to set t0 interval = 10 ms) b0bclr ft0ien ; to disable t0 interrupt service b0bclr ft0irq ; to clear t0 interrupt request b0bs et ft0enb ; to enable t0 timer ; go into green mode b0bclr fcpum0 ;to set cpumx = 10 b0bset fcpum1 ? note: during the green mode with t0 wake - up function, the wakeup pin and t0 wakeup the system back to the last mode. t0 wake - up period is controlled by program.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 61 version 1.6 5.3 wakeup 5.3.1 overview under power down mode (sleep mode) or green mode, program doesnt execute. the wakeup trigger can wake the system up to normal mode or slow mode. the wakeup trigger sources are external trigger (p0, p1 level change), internal trigger (t0 timer overflow) and usb bus toggle. ? power down mode is waked up to normal mode. the wakeup trigger is only external trigger (p0, p1 level change and usb bus toggle) ? green mode is waked up to last mode (normal mode or slow mo de). the wakeup triggers are external trigger (p0, p1 level change), internal trigger (t0 timer overflow) and usb bus toggle. 5.3.2 wakeup time when the system is in power down mode (sleep mode), the high clock oscillator stops. when waked up from power down mode, mcu waits for 16384 external 6mhz clocks as the wakeup time to stable the oscillator circuit. after the wakeup time, the system goes into the normal mode. ? note: wakeup from green mode is no wakeup time because the clock doesnt stop in green mode. the value of the wakeup time is as the following. D 16m_x tal/12m_x tal/6m_x tal mode: the wakeup time = 1/fosc * 16384 (sec) + high clock start - up time ? note: the high clock start - up time is depended on the vdd and oscillator type of high c lock. example: in 16m_x tal/12m_x tal/6m_x tal mode and power down mode (sleep mode), the system is waked up. after the wakeup time, the system goes into normal mode. the wakeup time is as the following. the wakeup time = 1/ 6mhz * 16384 = 2 . 7 2 ms t he total wakeup time = 2 . 7 2 ms + oscillator start - up time
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 62 version 1.6 6 interrupt 6.1 overview this mcu provides 15 interrupt sources, including 11 internal interrupt (t0/t 1 /tc0/tc1 / tc2/ usb/sio /msp/uart/ad/ io wakeup ) and 4 external interrupt (int0 /int1 / p0/p1 ). the external interrupt can wakeup the chip while the system is switched from power down mode to high - speed normal mode. once interrupt service is executed, the gie bit in stkp register will clear to D0 for stopping other interrupt request. on the contrast, when interrupt service exits, the gie bit will set to D1 to accept the next interrupts request. all of the interrupt request signals are stored in intrq register. ? note: the gie bit must enable during all in terrupt operation. i n t e n i n t e r r u p t e n a b l e r e g i s t e r i n t e r r u p t e n a b l e g a t i n g i n t r q 2 - b i t l a t c h s p 0 0 i r q t 0 i r q i n t e r r u p t v e c t o r a d d r e s s ( 0 0 0 8 h ) g l o b a l i n t e r r u p t r e q u e s t s i g n a l i n t 0 t r i g g e r t 0 t i m e o u t t 1 t i m e o u t u s b p r o c e s s e n d s i o t r a n s m i t r e a d y t 1 i r q u s b i r q s i o i r q i / o p i n w a k e u p t r i g g e r w a k e i r q p 0 1 i r q i n t 1 t r i g g e r t c 0 t i m e o u t t c 1 t i m e o u t t c 0 i r q t c 1 i r q t c 2 t i m e o u t t c 2 i r q t c 1 t i m e o u t t c 1 i r q m s p p r o c e s s m s p i r q u a r t p r o c e s s u a r t i r q a / d p r o c e s s a / d i r q p 0 t r i g g e r p 0 i r q p 1 t r i g g e r p 1 i r q
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 63 version 1.6 6.2 inten interrupt enable register inten is the interrupt request control register including one internal interrupts, one external interrupts enable control bits. one of the register to be set D1 is to enable the interrupt requ est function. once of the interrupt occur, the stack is incremented and program jump to org 8 to execute interrupt service routines. the program exits the interrupt service routine when the returning interrupt service routine instruction (reti) is executed . 0c7h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 inten1 p1ien p0ien mspien utrxien uttxien tc2ien tc1ien tc0ien read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 p1ien: p1 i/o level change interrupt control bit. 0 = disable p1 i/o level change interrupt function. 1 = enable p1 i/o level change interrupt function. bit 6 p0ien: p0 i/o level change interrupt control bit. 0 = disable p0 i/o level change interrupt function. 1 = enable p0 i/o level change interrupt fu nction. bit 5 mspien : msp function interrupt control bit. 0 = disable msp interrupt function. 1 = enable msp interrupt function. bit 4 utrxien: uart rx function interrupt control bit. 0 = disable uart rx interrupt function. 1 = enable uart rx interru pt function. bit 3 uttxien: uart tx function interrupt control bit. 0 = disable uart tx interrupt function. 1 = enable uart tx interrupt function. bit 2 tc2ien: tc2 timer function interrupt control bit. 0 = disable tc2 interrupt function. 1 = enable tc2 interrupt function. bit 1 tc1ien: tc1 timer interrupt control bit. 0 = disable tc1 interrupt function. 1 = enable tc1 interrupt function. bit 0 tc0ien: tc0 timer interrupt control bit. 0 = disable tc0 interrupt function. 1 = enable tc0 interrupt fu nction. 0c9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 inten adc ien usbien t 1 ien t0ien sioien wakeien p01ien p00ien read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 adcien: adc interrupt control bit. 0 = disable a dc interrupt function. 1 = enable adc interrupt function. bit 6 usbien: usb interrupt control bit. 0 = disable usb interrupt function. 1 = enable usb interrupt function.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 64 version 1.6 bit 5 t1ien: t1 timer interrupt control bit. 0 = disable t1 interrupt function. 1 = enable t1 interrupt function. bit 4 t0ien: t0 timer interrupt control bit. 0 = disable t0 interrupt function. 1 = enable t0 interrupt function. bit 3 sioien: sio interrupt control bit. 0 = disable sio interrupt function. 1 = enable sio interrupt func tion. bit 2 wakeien: i/o port0 & port 1 wakeup interrupt control bit. 0 = disable wakeup interrupt function. 1 = enable wakeup interrupt function. bit 1 p01ien: external p0.1 interrupt (int1) control bit. 0 = disable int1 interrupt function. 1 = enable int1 interrupt function. bit 0 p00ien: external p0.0 interrupt (int0) control bit. 0 = disable int0 interrupt function. 1 = enable int0 interrupt function.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 65 version 1.6 6.3 intrq interrupt request register intrq is the interrupt request flag register. the registe r includes all interrupt request indication flags. each one of the interrupt requests occurs; the bit of the intrq register would be set D1. the intrq value needs to be clear by programming after detecting the flag. in the interrupt vector of program, use rs know the any interrupt requests occurring by the register and do the routine corresponding of the interrupt request. 0c6h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intrq1 p1irq p0irq mspirq utrxirq uttxirq tc2irq tc1irq tc0irq read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 p1i rq : p1 i/o level change interrupt request flag. 0 = none p1 i/o level change interrupt request. 1 = p1 i/o level change interrupt request. bit 6 p0i rq : p0 i/o level change interrupt req uest flag. 0 = none p0 i/o level change interrupt request. 1 = p0 i/o level change interrupt request. bit 5 mspi rq : msp function interrupt request flag. 0 = none msp interrupt request. 1 = msp interrupt request. bit 4 utrxi rq : uart rx function interrup t request flag. 0 = none uart rx interrupt request. 1 = uart rx interrupt request. bit 3 uttxi rq : uart tx function interrupt request flag. 0 = none uart tx interrupt request. 1 = uart tx interrupt request. bit 2 tc2irq: tc2 timer function interrupt req uest flag. 0 = none tc2 interrupt request. 1 = t0 interrupt request. bit 1 tc1irq: tc1 timer interrupt request flag. 0 = none tc1 interrupt request. 1 = t0 interrupt request. bit 0 tc0irq: tc0 timer interrupt request flag. 0 = none tc0 interrupt reques t. 1 = t0 interrupt request. 0c8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intrq adc irq usbirq t 1 irq t0irq sioirq wakeirq p01irq p00irq read/write rw r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 adcirq: adc interrupt request flag. 0 = none adc interrupt request. 1 = adc interrupt request. bit 6 usbirq: usb interrupt request flag. 0 = none usb interrupt request. 1 = usb interrupt request.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 66 version 1.6 bit 5 t1irq: t1 timer interrupt request flag. 0 = none t1 interrupt request. 1 = t1 interrupt request. bit 4 t0irq: t0 timer interrupt request flag. 0 = none t0 interrupt request. 1 = t0 interrupt request. bit 3 sioirq: sio interrupt request flag. 0 = none sio interrupt request. 1 = sio interrupt request. bit 2 wakeir q: i/o port0 & port1 wakeup interrupt request flag. 0 = none wakeup interrupt request. 1 = wakeup interrupt request. bit 1 p01irq: external p0.1 interrupt (int1) request flag. 0 = none int0 interrupt request. 1 = int0 interrupt request. bit 0 p00irq: external p0.0 i nterrupt (int0) request flag. 0 = none int0 interrupt request. 1 = int0 interrupt request. 6.4 gie global interrupt operation gie is the global interrupt control bit. all interrupts start work after the gie = 1 it is necessary for interrupt service req uest. one of the interrupt requests occurs, and the program counter (pc) points to the interrupt vector (org 8) and the stack add 1 level. 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - - stkpb2 stkpb1 stkpb0 read/write r/w - - - - r/w r/w r/w after reset 0 - - - - 1 1 1 bit 7 gie: global interrupt control bit. 0 = disable global interrupt. 1 = enable global interrupt. example: set global interrupt control bit (gie). b0bset fgie ; enable gie ? note: the gie bit must enabl e during all interrupt operation. 6.5 push, pop routine when any interrupt occurs, system will jump to org 8 and execute interrupt service routine. it is necessary to save acc, pflag data. the chip includes Dpush, Dpop for in/out interrupt service ro utine. the two instructions save and load acc , pflag data into buffers and avoid main routine error after interrupt service routine finishing. ? note: push, pop instructions save and load acc/pflag without (nt0, npd). push/pop buffer is an unique buf fer and only one level.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 67 version 1.6 ? example: store acc and paflg data by push, pop instructions when interrupt service routine executed. org 0 jmp start org 8 jmp int_service org 10h start: push ; save acc and pflag to buffers. pop ; load acc and pflag from buffers. reti ; exit interrupt service vector
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 68 version 1.6 6.6 int0 (p0.0) & int1 (p0.1) interrupt operation when the int0 /int1 trigger occurs, the p00irq /p01ir q will be set to D1 no matter the p00ien /p01ien is enable or disable. if the p00ien /p01ien = 1 and the trigger event p00irq /p01irq is also set to be D1. as the result, the system will execute the interrupt vector (org 8). if the p00ien /p01ien = 0 and th e trigger event p00irq /p01irq is still set to be D1. moreover, the system wont execute interrupt vector even when the p00irq /p01irq is set to be D1. users need to be cautious with the operation under multi - interrupt situation. if the interrupt trigger direction is identical with wake - up trigger direction, the int0 /int1 interrupt request flag (int0irq /int1irq ) is latched while system wake - up from power down mode or green mode by p0.0 wake - up trigger. system inserts to interrupt vector (org 8) after wake - up immediately. ? note: int0 interrupt request can be latched by p0.0 wake - up trigger. ? note: int1 interrupt request can be latched by p0.1 wake - up trigger. ? note: the interrupt trigger direction of p0.0 /p0.1 is control by pedge register. 0bfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pedge p01g1 p01g0 p00g1 p00g0 read/write r/w r/w r/w r/w after reset 1 0 1 0 bit[3:2] p01g[1:0]: p0.1 interrupt trigger edge control bits. 00 = reserved. 01 = rising edge. 10 = falling edge. 11 = rising/falling bi - direction (level change trigger). bit[1 : 0 ] p00g[1:0]: p0.0 interrupt trigger edge control bits. 00 = reserved. 01 = rising edge. 10 = falling edge. 11 = rising/falling bi - direction (level change trigger). example: setup int0 interr upt request and bi - direction edge trigger. mov a, # 03 h b0mov pedge, a ; set int0 interrupt trigger as bi - direction edge. b0bset fp00ien ; enable int0 interrupt service b0bclr fp00irq ; clear int0 interrupt request flag b0bset fgie ; enable gie
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 69 version 1.6 example: int0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0bts1 fp00irq ; check p00irq jmp exit_int ; p00irq = 0, exit interrupt ve ctor b0bclr fp00irq ; reset p00irq ; int0 interrupt service routine
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 70 version 1.6 6.7 t0 interrupt operation when the t0c counter occurs over flow, the t0irq will be set to D1 however the t0ien is enable or disable. if the t0ien = 1, the trigger event will make the t0irq to be D1 and the system enter interrupt vector. if the t0ien = 0, the trigger event will make the t0irq to be D1 but the sy stem will not enter interrupt vector. users need to care for the operation under multi - interrupt situation. ? example: t0 interrupt request setup. b0bclr ft0ien ; disable t0 interrupt service b0bclr ft0enb ; disable t0 timer mov a, #20h ; b0mov t0m , a ; set t0 clock = fcpu / 64 mov a, #74h ; set t0c initial value = 74h b0mov t0c, a ; set t0 interval = 10 ms b0bset ft0ien ; enable t0 interrupt service b0bclr ft0irq ; clear t0 interrupt request flag b0bset ft0enb ; enable t0 timer b0bset fgie ; enable gie example: t0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0bts1 ft0irq ; check t0irq jmp exit_int ; t0irq = 0, exit interrupt vector b0bclr ft0irq ; reset t0irq mov a, #74h b0mov t0c, a ; reset t0c. ; t0 interrupt service routine
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 71 version 1.6 6.8 t 1 interrupt operation when the t1 c counter overflows, the t1 irq will be set to D1 no matter the t1 ien is enable or disable. if the t1 ien and the trigger event t1 irq is set to be D1. as the result, the system will execute the interrupt vector. if the t1 ien = 0, the trigger event t1 irq is still set to be D1. moreover, the system wont execute interrupt vector even when the t1 ien is set to be D1. users need to be cautious with the operation under multi - interrupt situation. ? example: t1 interrupt re quest setup. b0bclr f t1 ien ; disable t1 interrupt service b0bclr f t1 enb ; disable t1 timer mov a, #0 0 h ; b0mov t1 m, a ; set t1 clock = fcpu / 256 mov a, #0e5h ; set t1cl initial value = e5h b0mov t1cl, a mov a, #48h ; set t1ch initial value = 48h b0mov t1ch, a ; set t1 interval = 1s b0bset ft1ien ; enable t1 interrupt service b0bclr ft1irq ; clear t1 interrupt request flag b0bset ft1enb ; enable t1 timer b0bset fgie ; enable gie example: t1 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0bts1 f t1 irq ; check t1 irq jmp exit_int ; t1 irq = 0, exit interrupt vector b0bclr f t1 irq ; reset t1 irq mov a, # 0e 5 h b0mov t1 cl , a ; reset t1 c l . mov a, #48h b0mov t1ch, a ; reset t1ch. ; t1 interrupt service routine
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 72 version 1.6 6.9 tc0 interrupt operation when the tc0c counter overflows, the tc0irq will be set to D1 no matter the tc0ien is enable or disable. if the tc0ien and the trigger event tc0irq is set to be D1. as the result, the system will execute the interrupt vector. if the tc0ien = 0, the trigger event tc0irq is still set to be D1. moreover, the system wont execute interrupt vector even when the tc0ien is set to be D1. users need to be cautious with the operation under multi - interrupt situation. ? example: tc0 interrupt request set up. b0bclr ftc0ien ; disable tc0 interrupt service b0bclr ftc0enb ; disable tc0 timer mov a, #20h ; b0mov tc0m, a ; set tc0 clock = fcpu / 64 mov a, #74h ; set tc0c initial value = 74h b0mov tc0c, a ; set tc0 interval = 10 ms b0bset ftc 0ien ; enable tc0 interrupt service b0bclr ftc0irq ; clear tc0 interrupt request flag b0bset ftc0enb ; enable tc0 timer b0bset fgie ; enable gie ? example: tc0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_serv ice: b0bts1 ftc0irq ; check tc0irq jmp exit_int ; tc0irq = 0, exit interrupt vector b0bclr ftc0irq ; reset tc0irq mov a, #74h b0mov tc0c, a ; reset tc0c. ; tc0 interrup t service routine
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 73 version 1.6 6.10 tc1 interrupt operation when the tc1c counter overflows, the tc1irq will be set to D1 no matter the tc1ien is enable or disable. if the tc1ien and the trigger event tc1irq is set to be D1. as the result, the system will execute the interrupt vector. if the tc1ien = 0, the trigger event tc1irq is still set to be D1. moreover, the system wont execute interrupt vector even when the tc1ien is set to be D1. users need to be cautious with the operation under multi - interrupt situation. ? example: tc1 interrupt request setup. b0bclr ftc1ien ; disable tc1 interrupt service b0bclr ftc1enb ; disable tc1 timer mov a, #20h ; b0mov tc1m, a ; set tc1 clock = fcpu / 64 mov a, #74h ; set tc1c initial value = 74h b0mov tc1c, a ; set tc1 interval = 10 ms b0bset ftc1ien ; enable tc1 interrupt service b0bclr ftc1irq ; clear tc1 interrupt request flag b0bset ftc1enb ; enable tc1 timer b0bset fgie ; enable gie ? example: tc1 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0bts1 ftc1irq ; check tc1irq jmp exit_int ; tc1irq = 0, exit interrupt vector b0bclr ftc1irq ; reset tc1irq mov a, #74h b0mov tc1c, a ; reset tc1c. ; tc1 interrupt service routine
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 74 version 1.6 6.11 tc2 interrupt operation when the tc2c counter overflows, the tc2irq will be set to D1 no matter the tc2ien is enable or disable. if the tc2ien and the trigger event tc2irq is set to be D1. as the result, the sy stem will execute the interrupt vector. if the tc2ien = 0, the trigger event tc2irq is still set to be D1. moreover, the system wont execute interrupt vector even when the tc2ien is set to be D1. users need to be cautious with the operation under multi - interrupt situation. ? example: tc1 interrupt request setup. b0bclr ftc2ien ; disable tc2 interrupt service b0bclr ftc2enb ; disable tc2 timer mov a, #20h ; b0mov tc2m, a ; set tc2 clock = fcpu / 64 mov a, #74h ; set tc2c initial value = 74h b0 mov tc2c, a ; set tc2 interval = 10 ms b0bset ftc2ien ; enable tc2 interrupt service b0bclr ftc2irq ; clear tc2 interrupt request flag b0bset ftc2enb ; enable tc2 timer b0bset fgie ; enable gie ? example: tc1 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0bts1 ftc2irq ; check tc2irq jmp exit_int ; tc1irq = 0, exit interrupt vector b0bclr ftc2irq ; reset tc2irq mov a, #74h b0mov tc1c, a ; reset tc2c. ; tc2 interrupt service routine
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 75 version 1.6 6.1 2 usb interrupt operation when the usb process finished, the usb irq will be set to D1 no matter the usbien is enable or disable. if the usbien and the trigger event usbirq is set to be D1. as the result, the system will execute the interrupt vector. if the usbien = 0, the trigger event usbirq is still set to be D1. moreover, the system wont execute interrupt vector. users need to be cautious with the operation under multi - interrupt situation. ? example: usb interrupt request setup. b0bclr fusbien ; disable usb interrupt service b0bclr fusbirq ; clear usb interr upt request flag b0bset fusbien ; enable usb interrupt service example: usb interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: push ; push routine to save acc and pflag to buffers. b0bts1 fusbirq ; check usbirq jmp exit_int ; usbirq = 0, exit interrupt vector b0bclr fusbirq ; reset usbirq ; usb interrupt service routine
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 76 version 1.6 6.1 3 wakeup interrupt operation when the i/o port 1 or i/o port 0 wakeup the mcu from the sleep mode, the wakeirq will be set to D1 no matter the wake ien is enable or disable. if the wakeien and the trigger event wakeirq is set to be D1. as the result, the system will execute the interrupt vector. if the wakeien = 0, the trigger event wakeirq is still set to be D1. moreover, the system wont execute interrupt vector. users need to be cautious with the operation under multi - interrupt situation. ? example: wake interrupt request setup. b0bclr fwakeien ; disable wake interrupt service b0bclr fwakeirq ; clear wake interrupt request flag b0bset fwake ien ; enable wake interrupt service example: wake interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: push ; push routine to save acc and pflag to buffers. b0bts1 fwakeirq ; check wakeirq jmp exit_int ; wakeirq = 0, exit interrupt vector b0bclr fwakeirq ; reset wakeirq ; wake interrupt service routine
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 77 version 1.6 6.1 4 sio interrupt operation when the sio converting successfully, the sioirq will be set to D1 no matter the sioien is enable or disable. if the sioien and the trigger eve nt sioirq is set to be D1. as the result, the system will execute the interrupt vector. if the sioien = 0, the trigger event sioirq is still set to be D1. moreover, the system wont execute interrupt vector even when the sioien is set to be D1. users need to be cautious with the operation under multi - interrupt situation. ? example: sio interrupt request setup. b0bset fsioien ; enable sio interrupt service b0bclr fsioirq ; clear sio interrupt request flag b0bset fgie ; enable gie ? example: sio i nterrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0bts1 fsioirq ; check sioirq jmp exit_int ; sioirq = 0, exit interrupt vector b0bclr fsioirq ; reset sioirq ; sio interrupt service routine
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 78 version 1.6 6.1 5 multi - interrupt operation under certain condition, the software des igner uses more than one interrupt requests. processing multi - interrupt request requires setting the priority of the interrupt requests. the irq flags of interrupts are controlled by the interrupt event. nevertheless, the irq flag D1 doesnt mean the syst em will execute the interrupt vector. in addition, which means the irq flags can be set D1 by the events without enable the interrupt. once the event occurs, the irq will be logic D1. the irq and its trigger event relationship is as the below table. inte rrupt name trigger event description p00irq p0.0 trigger controlled by pedge t0irq t0c overflow t1 irq t1 c overflow usbirq usb process finished waekirq i/o port0 & port1 wakeup mcu sioirq sio process finished for multi - interrupt conditions, two thing s need to be taking care of. one is to set the priority for these interrupt requests. two is using ien and irq flags to decide which interrupt to be executed. users have to check interrupt control bit and interrupt request flag in interrupt routine. ? exampl e: check the interrupt request under multi - interrupt operation org 8 ; interrupt vector jmp int_service int_service: ; push routine to save acc and pflag to buffers. intp00chk: ; check int0 interrupt request b0bts1 fp00ien ; ch eck p00ien jmp intt0chk ; jump check to next interrupt b0bts0 fp00irq ; check p00irq jmp intp00 intt0chk: ; check t0 interrupt request b0bts1 ft0ien ; check t0ien jmp int t1 chk ; jump check to next interrupt b0bts0 ft0irq ; check t0irq jmp intt0 ; jump to t0 interrupt service routine int t1 chk: ; check t1 interrupt request b0bts1 f t1 ien ; check t1 ien jmp inttc1chk ; jump check to next interrupt b0bts0 f t1 irq ; check t1 irq jmp int t1 ; jump to t1 interrupt service routine intusbchk : ; check usb interrupt request b0bts1 fusbien ; check usbien jmp intwakechk ; jump check to next interrupt b0bts0 fusbirq ; check usbirq jmp intusb ; jump to usb interrupt service routine intwakechk: ; check usb interrupt request b0bts1 fwa keien ; check wakeien jmp intsiochk ; jump check to next interrupt b0bts0 fwakeirq ; check wakeirq jmp intwakeup ; jump to wakeup interrupt service routine intsiochk: ; check sio interrupt request b0bts1 fsioien ; check sioien jmp int_exit ; j ump check to next interrupt b0bts0 fsioirq ; check sioirq jmp intsio ; jump to sio interrupt service routine int_exit: ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 79 version 1.6 7 i/o port 7.1 i/o port mode the port direction is programmed by pnm register. all i/o ports can select input or output direction. 0b8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0m p07m p06m p05m p04m p03m p02m p01m p00m read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0c1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1m p17m p16m p15m p14m p13m p12m p11 m p10m read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0c2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2m p27m p26m p25 m p24m p23m p22m p21m p20m read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0c4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4m p47m p46m p45m p44m p43m p42m p41m p40m read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0c5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5m - - p55m p54m p53m p52m p51m p50m read/write - - r/w r/w r/w r/w r/w r/w after reset - - 0 0 0 0 0 0 bit[7:0] pnm[7:0]: pn mode control bits. (n = 0~ 3 ). 0 = pn is input mode . 1 = pn is output mode. ? note: 1. users can program them by bit control instructions (b0bset, b0bclr). ? example: i/o mode selecting clr p0m ; set all ports to be input mode. clr p1m clr p5m mov a, #0ffh ; set all ports to be output mode. b0mov p0m, a b0mov p1m, a b0mov p5m, a b0bclr p1m.2 ; set p1.2 to be input mode. b0bset p1m.2 ; set p1.2 to be output mode.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 80 version 1.6 7.2 i/o pull up register 0e0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0ur p07r p06r p05r p00r p03r p02r p01r p00r read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 0e1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1ur p17r p16r p15r p16r p13r p12r p11r p10r read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 0e2h bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 p2ur p27r p26r p25r p24r p23r p22r p21r p20r read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 0e4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4ur p47r p46r p45r p44r p43r p42r p41r p40r read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 0e5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5ur - - p55r p54r p53r p52r p51r p50r read/write - - w w w w w w after reset - - 0 0 0 0 0 0 ? note: p0. 4 is input only pin with pull - up resister. ? example: i /o pull up register mov a, #0ffh ; enable port0, 1, 5 pull - up register, b0mov p0ur, a ; b0mov p1ur, a b0mov p5ur, a
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 81 version 1.6 7.3 i/o open - drain register p1.0/p1.1 /p0.6/p0.5 is built - in open - drain function. p1.0/p1.1/p0.6/p0.5 must be se t as output mode when enable p1.0/p1.1/p0.6/p0.5 open - drain function. open - drain external circuit is as following. the pull - up resistor is necessary. open - drain output high is driven by pull - up resistor. output low is sunken by mcu s pin. 0 e 9h bit 7 bi t 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p 1oc - - - - p 06oc p 05oc p 11oc p 1 0 oc read/write - - - - w w w w after reset - - - - 0 0 0 0 bit [3:2] p0noc : port 0 open - drain control bit 0 = d isable open - drain mode 1 = e nable open - drain mode bit [1: 0 ] p1noc : port 1 open - drain control bit 0 = d isable open - drain mode 1 = e nable open - drain mode ? example: enable p1.0 to open - drain mode and output high. b0bset p1.0 ; set p1.0 buffer high. b0bset p10m ; enable p1.0 output mode. mov a, #01h ; enable p 1.0 open - drain function. b0mov p1oc, a ? note : p1oc is write only register. setting p10oc must be used mov instructions . ? example: disable p1.0 to open - drain mode and output low. mov a, #0 ; disable p 1.0 open - drain function. b0mov p1oc, a ? note : after disable p1.0 open - drain function , p1.0 mode returns to last i/o mode. u mcu2 u vcc open-drain pin open-drain pin mcu1 pull-up resistor
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 82 version 1.6 7. 4 i/o port data register 0d0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 p07 p06 p05 p04 p03 p02 p01 p00 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0d1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1 p17 p16 p15 p14 p13 p12 p11 p10 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0d2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2 p27 p26 p25 p24 p23 p22 p21 p20 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0d4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4 p47 p46 p45 p44 p43 p42 p41 p40 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0d5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5 - - p55 p54 p53 p52 p51 p50 read/write - - r/w r/w r/w r/w r/w r/w after reset - - 0 0 0 0 0 0 ? example: read data from input port. b0mov a, p0 ; read data from port 0 b0mov a, p 1 ; read data from port 1 b0mov a, p5 ; read data from port 5 ? example: write data to output port. mov a, #0ffh ; write data ffh to all port. b0mov p0, a b0mov p1, a b0mov p5, a ? example: write one bit data to output port. b0bset p1.3 ; set p1.3 and p5. 3 to be D1. b0bset p5. 3 b0bclr p1.3 ; set p1.3 and p5. 3 to be D0. b0bclr p5. 3
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 83 version 1.6 7. 5 i/o port1 wakeup control register 0 c 0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1w p17w p16w p15w p14w p13w p12w p11w p10w rea d/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit [7:0] p1 n w: port 1 wakeup function control bit . 0 = disable port 1 wakeup function . 1 = enable port 1 wakeup function .
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 84 version 1.6 8 timers 8.1 watchdog timer the watchdog timer (wdt) is a binary up counter designed for monitoring program execution. if the program goes into the unknown status by noise interference, wdt overflow signal raises and resets mcu. watchdog clock controlled by code option and the clock source is internal low - speed oscillator ( 12 khz ). watchdog overflow time = 8192 / internal low - speed oscillator (sec). vdd internal low rc freq. code option C 5v 12khz flosc/2 341ms 5v 12khz flosc /4 682ms ? note: if watchdog is always_on mode, it keeps running event under power down mode or green mode. watchdog clear is controlled by wdtr register. moving 0x5a data into wdtr is to reset watchdog timer. 0cch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wdtr wdtr7 wdtr6 wdtr5 wdtr4 wdtr3 wdtr2 wdtr1 wdtr0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 example: an operation of watchdog timer is as following. to clear the watchdog timer counter in the top of the main routine of the program. main: mov a,#5ah ; clear the watchdog timer. b0mov wdtr,a
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 85 version 1.6 watchdog timer application note is as following. ? before clearing watchdog timer, check i/o status and check ram contents can improve system error. ? dont clear watchdog timer in interrupt vector and interrupt service routine. that can improve main routine fail. ? clearing watchdog timer program is only at one part of the program. this way is the best structure to enhance the watchdog timer function. ? example: an operation of watchdog timer is as following. to clear the watchdog timer counter in the top of the main routine of the program. main: program jump here and dont
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 86 version 1.6 8.2 timer 0 (t0) 8.2.1 overview the t0 is an 8 - bit binary up timer and event counter. if t0 timer occurs an overflow (from ffh to 00h), it will continue counting and issue a time - out signal to trigg er t0 interrupt to request interrupt service. the main purpose of the t0 timer is as following. ? 8 - bit programmable up counting timer: generates interrupts at specific time intervals based on the selected clock frequency. ? green mode wakeup function: t0 c an be green mode wake - up time as t0enb = 1. system will be wake - up by t0 time out. 8.2.2 t0m mode register 0d8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0m t0enb t0rate2 t0rate1 t0rate0 - - - read/write r/w r/w r /w r/w - - - after reset 0 0 0 0 - - - bit 7 t0enb: t0 counter control bit. 0 = disable t0 timer. 1 = enable t0 timer. bit [6:4] t0rate[2:0]: t0 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. 110 = fcpu/4. 111 = fcpu/2. fcpu t0 rate (fcpu/2~fcpu/256) t0enb cpum0,1 t0c 8-bit binary up counting counter t0 time out load internal data bus
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 87 version 1.6 8.2.3 t0c counting register t0c is an 8 - bit counter register for t0 interval time control. 0d9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0c t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of t0c initial value is as following. t0c initial value = 256 - (t0 interrupt interval time * input clock) example: to set 1ms interval time for t0 interrupt. high clock is 12 mhz. fcpu=fosc/ 2 . select t0rate=010 (fcpu/64). t0c initial value = 256 - (t0 interrupt interval time * input clock) = 256 - (1ms * 6mhz / 1 / 64) = 256 - (10 - 3 * 6 * 10 6 / 1 / 64) = 162 = a2h the basic timer table interval time of t0. t0rate t0clock high speed mode (fcpu = 12 mhz / 2 ) max overflow int erval one step = max/256 000 fcpu/256 10.923 ms 42.67 us 001 fcpu/128 5.461 ms 21.33 us 010 fcpu/64 2.731 ms 10.67 us 011 fcpu/32 1.365 ms 5.33 us 100 fcpu/16 0.683 ms 2.67 us 101 fcpu/8 0.341 ms 1.33 us 110 fcpu/4 0.171 ms 0.67 us 111 fcpu/2 0.085 ms 0.33 us
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 88 version 1.6 8.2.4 t0 timer operation sequence t0 timer operation sequence of setup t0 timer is as following. ? stop t0 timer counting, disable t0 interrupt function and clear t0 interrupt request flag. b0bclr ft0enb ; t0 timer. b0b clr ft0ien ; t0 interrupt function is disabled. b0bclr ft0irq ; t0 interrupt request flag is cleared. ? set t0 timer rate. mov a, #0xxx0000b ;the t0 rate control bits exist in bit4~bit6 of t0m. the ; value is from x000xxxxb~x111xxxxb. b0mov t0m, a ; t0 timer is disabled. ? set t0 interrupt interval time. mov a,#7fh b0mov t0c,a ; set t0c value. ? set t0 timer function mode. b0bset ft0ien ; enable t0 interrupt function. ? enable t0 timer. b0bset ft0enb ; enable t0 timer.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 89 version 1.6 8.3 timer t1 ( t1 ) 8.3.1 overview the t1 is a 16 - bit binary up timer and event counter. if t1 timer occurs an overflow (from ff ff h to 00 00 h), it will continue counting and issue a time - out signal to trigger t1 interrupt to request interrupt service. the main purpo se of the t1 timer is as following. ? 16 - bit programmable up counting timer: generates interrupts at specific time intervals based on the selected clock frequency. ? green mode wakeup function: t1 can be green mode wake - up time as t1 enb = 1. system will be wa ke - up by t1 time out. 8.3.2 t1 m mode register 0dah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t1 m t1 enb t1 rate2 t1 rate1 t1 rate0 - - - read/write r/w r/w r/w r/w - - - after reset 0 0 0 0 - - - bit 7 t1enb: t1 counter control bit. 0 = disable t1 timer. 1 = enable t1 timer. bit [6:4] t1 rate[2:0]: t1 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. 110 = fcpu/4. 111 = fcpu/2. fcpu t1 rate (fcpu/2~fcpu/256) t1enb cpum0,1 t1c 16-bit binary up counting counter t1 time out load internal data bus
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 90 version 1.6 8.3.3 t1 c counting register t1 c l with t1ch is an 16 - bit counter re gister for t1 interval time control. 0dbh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t1 c l t1 c7 t1 c6 t1 c5 t1 c4 t1 c3 t1 c2 t1 c1 t1 c0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0dch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bi t 1 bit 0 t1ch t1c15 t1c14 t1c13 t1c12 t1c11 t1c10 t1c9 t1c8 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of t1 c initial value is as following. t1 c initial value = 65536 - ( t1 interrupt interval time * input clock) example: to set 1ms interval time for t1 interrupt. high clock is 12 mhz. fcpu=fosc/ 2 . select t1 rate=0 0 1 (fcpu/ 128 ). t1 c initial value = 655 3 6 - ( t1 interrupt interval time * input clock) = 6553 6 - (1s * 12 mhz / 2 / 128 ) = 65536 - (10 * 6 * 10 6 / 1 / 128 ) = 18661 = 48e5 h the basic timer table interval time of t1. t1rate t1clock high speed mode (fcpu = 12mhz / 2) max overflow interval one step = max/256 000 fcpu/256 2.796 s 42.67 us 001 fcpu/128 1.398 s 21.33 us 010 fcpu/64 699.051 ms 10.67 us 011 fcpu/32 349.525 ms 5.33 us 100 fcpu/16 174.763 ms 2.67 us 101 fcpu/8 87.381 ms 1.33 us 110 fcpu/4 43.691 ms 0.67 us 111 fcpu/2 21.845 ms 0.33 us 8.3.4 t1 timer operation sequence t1 timer operation sequence of setup t1 timer is as fol lowing. ? stop t1 timer counting, disable t1 interrupt function and clear t1 interrupt request flag. b0bclr f t1 enb ; t1 timer. b0bclr f t1 ien ; t1 interrupt function is disabled. b0bclr f t1 irq ; t1 interrupt request flag is cleared.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 91 version 1.6 ? set t1 timer r ate. mov a, #0xxx0000b ;the t1 rate control bits exist in bit4~bit6 of t1 m. the ; value is from x000xxxxb~x111xxxxb. b0mov t1 m,a ; t1 timer is disabled. ? set t1 interrupt interval time. mov a,#0e5 h b0mov t1 c l ,a ; set t1 c l value. mov a,#48h b0mov t1ch,a ; set t1ch value. ? set t1 timer function mode. b0bset f t1 ien ; enable t1 interrupt function. ? enable t1 timer. b0bset f t1 enb ; enable t1 timer.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 92 version 1.6 8.4 timer/counter 0 (tc0 ~tc2 ) 8.4.1 overview the tc n (n=0 , 1, 2 ) is an 8 - bit binary up counting timer with double buffers. tc n has two clock sources including internal clock and external clock for counting a precision time. the internal clock source is from fcpu. the external clock is int0 from p0.0 pin (falling edge trigger). using tc n m register selects tc n cs clock source from internal or external. if tc n timer occurs an overflow, it will continue counting and issue a time - out signal to trigger tcn interrupt to request interrupt service. tcn overflo w time is 0xff to 0x00 normally. under pwm mode, tcn overflow is decided b y pwm cycle controlled by aloadn (n=0, 1, 2) and tcn out bits. the main purposes of the tcn timer are as following. ? 8 - bit programmable up counting timer: generates interrupts at spe cific time intervals based on the selected clock frequency. ? external event counter: counts system Devents based on falling edge detection of external clock signals at the int0 input pin. ? buzzer output ? pwm output f c p u t c n r a t e ( f c p u / 2 ~ f c p u / 2 5 6 ) i n t 0 ( s c h m i t t e r t r i g g e r ) t c n c k s t c n e n b c p u m 0 , 1 t c n c 8 - b i t b i n a r y u p c o u n t i n g c o u n t e r t c n r r e l o a d d a t a b u f f e r u p c o u n t i n g r e l o a d v a l u e t c n t i m e o u t c o m p a r e a l o a d n r s t c n t i m e o u t a u t o . r e l o a d t c n / 2 b u z z e r i n t e r n a l i / o c i r c u i t i / o p w m p w m n o u t t c n o u t a l o a d n , t c n o u t l o a d
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 93 version 1.6 8.4.2 tcn m mode register 0 88 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0 m tc0 enb tc0 rate2 tc0 rate1 tc0 rate0 tc0 cks aload 0 tc0 out pwm0out read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 tc0enb: tc0 counter control bit. 0 = disable tc0 timer. 1 = enable tc0 timer. bit [6:4] tc0rate[2:0]: tc0 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. 110 = fcpu/4. 111 = fcpu/2. bit 3 tc0cks: tc0 clock source select bit. 0 = internal clock (fcpu or fosc). 1 = e xternal clock from p0.0/int0 pin. bit 2 aload0: auto - reload control bit. only valid when pwm0out = 0. 0 = disable tc0 auto - reload function. 1 = enable tc0 auto - reload function. bit 1 tc0out: tc0 time out toggle signal output control bit. only valid when pwm0out = 0. 0 = disable, p5.3 is i/o function. 1 = enable, p5.3 is output tc0out signal. bit 0 pwm0out: pwm output control bit. 0 = disable pwm output. 1 = enable pwm output. pwm duty controlled by tc0 out, aload0 bits. ? note: when tc 0 cks=1, tc 0 be came an external event counter and tc 0 rate is useless. no more p0.0 interrupt request will be raised. (p0.0irq will be always 0). 08bh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1m tc1enb tc1rate2 tc1rate1 tc1rate0 tc1cks aload1 tc1out pwm1ou t read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 tc1enb: tc1 counter control bit. 0 = disable tc1 timer. 1 = enable tc1 timer. bit [6:4] tc1rate[2:0]: tc1 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. 110 = fcpu/4. 111 = fcpu/2. bit 3 tc1cks: tc1 clock source select bit. 0 = internal clock (fcpu or fosc).
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 94 version 1.6 1 = external clock from p0.1/int1 pin. bit 2 aload1: auto - reload control bit. only valid when pwm1out = 0. 0 = disable tc1 auto - reload functi on. 1 = enable tc1 auto - reload function. bit 1 tc1out: tc1 time out toggle signal output control bit. only valid when pwm1out = 0. 0 = disable, p5.4 is i/o function. 1 = enable, p5.4 is output tc0out signal. bit 0 pwm1out: pwm output control bit. 0 = disable pwm output. 1 = enable pwm output. pwm duty controlled by tc1out, aload1 bits. ? note: when tc1cks=1, tc0 became an external event counter and tc1rate is useless. no more p0.1 interrupt request will be raised. (p0.1irq will be always 0). 08eh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc2m tc2enb tc2rate2 tc2rate1 tc2rate0 tc2cks aload2 tc2out pwm2out read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 tc2enb: tc2 counter control bit. 0 = disable tc2 ti mer. 1 = enable tc2 timer. bit [6:4] tc2rate[2:0]: tc2 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. 110 = fcpu/4. 111 = fcpu/2. bit 3 tc2cks: tc2 clock source select bit. 0 = internal clock (fcpu or fosc). 1 = external clock fro m p0.2 pin. bit 2 aload2: auto - reload control bit. only valid when pwm2out = 0. 0 = disable tc2 auto - reload function. 1 = enable tc2 auto - reload function. bit 1 tc2out: tc2 time out toggle signal output control bit. only valid when pwm2out = 0. 0 = dis able, p5.5 is i/o function. 1 = enable, p5.5 is output tc2out signal. bit 0 pwm2out: pwm output control bit. 0 = disable pwm output. 1 = enable pwm output. pwm duty controlled by tc2out, aload2 bits.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 95 version 1.6 8.4.3 tcn c counting register tcn c (n = 0, 1, 2) is an 8 - bit counter register for tcn interval time control. 0 89 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc 0 c tc 0 c7 tc 0 c6 tc 0 c5 tc 0 c4 tc 0 c3 tc 0 c2 tc 0 c1 tc 0 c0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 08ch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1c tc1c7 tc1c6 tc1c5 tc1c4 tc1c3 tc1c2 tc1c1 tc1c0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 08fh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc2c tc2c7 tc2c6 tc2c5 tc2c4 tc2c3 tc2c2 tc2c1 tc2c0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of tcn c initial value is as following. tcn c initial value = n - ( tcn interrupt interval time * input clock) n is tcn overflow boundary nu mber. tcn timer overflow time has six types ( tcn timer, tcn event counter, tcn fcpu clock source, tcn fosc clock source, pwm mode and no pwm mode). these parameters decide tcn overflow time and valid value as follow table. tcn cks pwmn aloadn tcn out n tcn c valid value tcn c value binary type remark 0 0 x x 256 0x00~0xff 00000000b~11111111b overflow per 256 count 1 0 0 256 0x00~0xff 00000000b~11111111b overflow per 256 count 1 0 1 64 0x00~0x3f xx000000b~xx111111b overflow per 64 count 1 1 0 32 0x00~0x1 f xxx00000b~xxx11111b overflow per 32 count 1 1 1 16 0x00~0x0f xxxx0000b~xxxx1111b overflow per 16 count 1 - - - 256 0x00~0xff 00000000b~11111111b overflow per 256 count ? example: to set 1ms interval time for tcn interrupt. tcn clock source is fcpu ( tc n ks=0) and no pwm output (pwm n =0). high clock is internal 6mhz. fcpu=fosc/ 2 . select tcn rate=010 (fcpu/64). tcn c initial value = n - ( tcn interrupt interval time * input clock) = 256 - (1ms * 6mhz / 1 / 64) = 256 - (10 - 3 * 6 * 10 6 / 1 / 64) = 162 = a2h t he basic timer table interval time of tcn . tcn rate tcn clock high speed mode (fcpu = 6mhz / 1) max overflow interval one step = max/256 000 fcpu/256 10.923 ms 42.67 us 001 fcpu/128 5.461 ms 21.33 us 010 fcpu/64 2.731 ms 10.67 us 011 fcpu/32 1.365 ms 5.33 us 100 fcpu/16 0.683 ms 2.67 us 101 fcpu/8 0.341 ms 1.33 us 110 fcpu/4 0.171 ms 0.67 us 111 fcpu/2 0.085 ms 0.33 us
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 96 version 1.6 8.4.4 tcn r auto - load register tcn (n = 0, 1, 2) timer is with auto - load function controlled by aload n (n = 0, 1, 2) bit of tcn m (n = 0, 1, 2) . when tcn c (n = 0, 1, 2) overflow occurring, tcn r (n = 0, 1, 2) value will load to tcn c by system. it is easy to generate an accurate time, and users dont reset tcn c during interrupt service routine. tcn is double buffer design. if new t cn r value is set by program, the new value is stored in 1 p st p buffer. until tcn overflow occurs, the new value moves to real tcn r buffer. this way can avoid tcn interval time error and glitch in pwm and buzzer output. ? note: under pwm mode, auto - load is e nabled automatically. the aload n bit is selecting overflow boundary. 0 8a h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0 r tc0 r7 tc0 r6 tc0 r5 tc0 r4 tc0 r3 tc0 r2 tc0 r1 tc0 r0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 08dh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1 r tc1 r7 tc1 r6 tc1 r5 tc1 r4 tc1 r3 tc1 r2 tc1 r1 tc1 r0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 090h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc2 r tc2 r7 tc2 r6 tc2 r5 tc2 r4 tc2 r3 tc2 r2 tc2 r1 tc2 r0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 the equation of tcn r initial value is as following. tcn r initial value = n - ( tcn interrupt interval time * input clock) n is tcn overflow boundary number. tcn timer overflow time has six ty pes ( tcn timer, tcn event counter, tcn fcpu clock source, tcn fosc clock source, pwm mode and no pwm mode). these parameters decide tcn overflow time and valid value as follow table. tcn cks pwm n aload n tcn out n tcn r valid value tcn r value binary type 0 0 x x 256 0x00~0xff 00000000b~11111111b 1 0 0 256 0x00~0xff 00000000b~11111111b 1 0 1 64 0x00~0x3f xx000000b~xx111111b 1 1 0 32 0x00~0x1f xxx00000b~xxx11111b 1 1 1 16 0x00~0x0f xxxx0000b~xxxx1111b 1 - - - 256 0x00~0xff 00000000b~11111111b ? exampl e: to set 1ms interval time for tcn interrupt. tcn clock source is fcpu ( tcn ks=0) and no pwm output (pwm n =0). high clock is internal 6 mhz. fcpu=fosc/2 . select tcn rate=010 (fcpu/64). tcn r initial value = n - ( tcn interrupt interval time * input clock) = 2 56 - (1ms * 6mhz / 1 / 64) = 256 - (10 - 3 * 6 * 10 6 / 1 / 64) = 162 = a2h
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 97 version 1.6 8.4.5 tcn clock frequency output (buzzer) buzzer output ( tcn out) is from tcn timer/counter frequency output function. if setting the tc 0 clock frequency, the clock signal is outpu t to p5. 3 and the p5. 3 general purpose i/o function is auto - disable. the tcn out frequency is divided by 2 from tcn interval time. tcn out frequency is 1/2 tcn frequency. the tcn clock has many combinations and easily to make difference frequency. the tcn out frequency waveform is as following. ? example: setup tc 0 out output from tc 0 to tc 0 out (p5. 3 ). the external high - speed clock is 4mhz. the tc 0 out frequency is 0.5khz. because the tc0 out signal is divided by 2, set the tc 0 c lock to 1khz. the tc 0 clock source is from external oscillator clock. t0c rate is fcpu/4. the tc 0 rate2~ tc 0 rate1 = 110. tc 0 c = tcn r = 131. mov a,#01100000b b0mov tc 0 m,a ; set the tc 0 rate to fcpu/4 mov a,#131 ; set the auto - reload reference val ue b0mov tc 0 c,a b0mov tc 0 r,a b0bset f tc 0 out ; enable tc 0 output to p5. 3 and disable p5. 3 i/o function b0bset faload 0 ; enable tc 0 auto - reload function b0bset f tc 0 enb ; enable tc 0 timer ? note: buzzer output is enable, and pwm0out must be 0. 1 2 3 4 1 2 3 4 t c n o v e r f l o w c l o c k t c n o u t ( b u z z e r ) o u t p u t c l o c k
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 98 version 1.6 8.4.6 tcn timer operation sequence tcn timer operation includes timer interrupt, event counter, tcn out and pwm. the sequence of setup tc 0 timer is as following. ? stop tc0 timer counting, disable tc0 interrupt function and clear tc0 inte rrupt request flag. b0bclr f tc0 enb ; tc0 timer, tc0 out and pwm stop. b0bclr f tc0 ien ; tc0 interrupt function is disabled. b0bclr f tc0 irq ; tc0 interrupt request flag is cleared. ? set tc0 timer rate. (besides event counter mode.) mov a, #0xxx0000b ;the tc0 rate control bits exist in bit4~bit6 of tc0 m. the ; value is from x000xxxxb~x111xxxxb. b0mov tc0 m,a ; tc0 interrupt function is disabled. ? set tc0 timer clock source. ; select tc0 internal / external clock source. b0bclr f tc0 cks ; selec t tc0 internal clock source. or b0bset f tc0 cks ; select tc0 external clock source. ? set tc0 timer auto - load mode. b0bclr faload0 ; enable tc0 auto reload function. or b0bset faload0 ; disable tc0 auto reload function. ? set tc0 interrup t interval time, tc0 out (buzzer) frequency or pwm duty cycle. ; set tc0 interrupt interval time, tc0 out (buzzer) frequency or pwm duty. mov a,#7fh ; tc0 c and tc0 r value is decided by tc0 mode. b0mov tc0 c,a ; set tc0 c value. b0mov tc0 r,a ; set tc0 r v alue under auto reload mode or pwm mode. ; in pwm mode, set pwm cycle. b0bclr faload0 ; aload0, tc0 out = 00, pwm cycle boundary is b0bclr f tc0 out ; 0~255. or b0bclr faload0 ; aload0, tc0 out = 01, pwm cycle boundary is b0bset f tc0 out ; 0 ~63. or b0bset faload0 ; aload0, tc0 out = 10, pwm cycle boundary is b0bclr f tc0 out ; 0~31. or b0bset faload0 ; aload0, tc0 out = 11, pwm cycle boundary is b0bset f tc0 out ; 0~15. ? set tc0 timer function mode. b0bset f tc0 ien ; enable tc0 interrupt function. or b0bset f tc0 out ; enable tc0 out (buzzer) function. or b0bset fpwm0out ; enable pwm function. ? enable tc0 timer. b0bset f tc0 enb ; enable tc0 timer.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 99 version 1.6 8.5 pwm n mode 8.5.1 overview pwm function is generated by tcn timer counter and output the pwm signal to pwm0out pin (p5.3 ) , pwm1out pin (p5.4) pwm2out pin (p5.5) . the 8 - bit counter counts modulus 256, 64, 32, 16 controlled by aload n , tcn out bits. the value of the 8 - bit counter ( tcn c) is compared to the contents of the ref erence register ( tcn r). when the reference register value ( tcn r) is equal to the counter value ( tcn c), the pwm output goes low. when the counter reaches zero, the pwm output is forced high. the low - to - high ratio (duty) of the pwm n output is tcn r/256, 64, 3 2, 16. pwm output can be held at low level by continuously loading the reference register with 00h. under pwm operating, to change the pwms duty cycle is to modify the tcn r. ? note: tcn is double buffer design. modifying tcn r to change pwm duty by prog ram, there is no glitch and error duty signal in pwm output waveform. users can change tcn r any time, and the new reload value is loaded to tcn r buffer at tcn overflow. aload n tcn out pwm duty range tcn c valid value tcn r valid bits value max. pwm frequ ency (fcpu = 6mhz) remark 0 0 0/256~255/256 0x00~0xff 0x00~0xff 11.719k overflow per 256 count 0 1 0/64~63/64 0x00~0x3f 0x00~0x3f 46.875k overflow per 64 count 1 0 0/32~31/32 0x00~0x1f 0x00~0x1f 93.75k overflow per 32 count 1 1 0/16~15/16 0x00~0x0f 0x0 0~0x0f 187.5k overflow per 16 count the output duty of pwm is with different tcn r. duty range is from 0/256~255/256. t c n c l o c k t c n r = 0 0 h t c n r = 0 1 h t c n r = 8 0 h t c n r = f f h 0 1 1 2 8 2 5 4 2 5 5 0 1 1 2 8 2 5 4 2 5 5 l o w l o w l o w h i g h h i g h l o w h i g h
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 100 version 1.6 8.5.2 tc n irq and pwm duty in pwm mode, the frequency of tcn irq is depended on pwm duty range. from fo llowing diagram, the tcn irq frequency is related with pwm duty. t c n o v e r f l o w , t c n i r q = 1 p w m n o u t p u t ( d u t y r a n g e 0 ~ 1 5 ) 0 x f f t c n c v a l u e 0 x 0 0 p w m n o u t p u t ( d u t y r a n g e 0 ~ 3 1 ) 0 x f f t c n c v a l u e 0 x 0 0 p w m n o u t p u t ( d u t y r a n g e 0 ~ 6 3 ) 0 x f f t c n c v a l u e 0 x 0 0 0 x f f t c n c v a l u e 0 x 0 0 p w m n o u t p u t ( d u t y r a n g e 0 ~ 2 5 5 ) t c n o v e r f l o w , t c n i r q = 1 t c n o v e r f l o w , t c n i r q = 1 t c n o v e r f l o w , t c n i r q = 1
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 101 version 1.6 8.5.3 pwm duty with tc n r changing in pwm mode, the system will compare tcn c and tcn r all the time. when tcn c< tcn r, the pwm will output logic Dhigh, when tcn c R tcn r, the pwm will output logic Dlow. if tcn c is changed in certain period, the pwm duty will change in next pwm period. if tcn r is fixed all the time, the pwm waveform is also the same. above diagram is shown the wavefor m with fixed tcn r. in every tcn c overflow pwm output Dhigh, when tcn c R tcn r pwm output low. if tcn r is changing in the program processing, the pwm waveform will became as following diagram. in period 2 and period 4, new duty ( tcn r) is set. tcn is double buffer design. the pwm still keeps the same duty in period 2 and period 4, and the new duty is changed in next period. by the way, system can avoid the pwm not changing or h/l changing twice in the same cycle and will prevent the unexpected or error operation. t c n c o v e r f l o w a n d t c n i r q s e t t c n c = t c n r 0 x f f t c n c v a l u e 0 x 0 0 p w m n o u t p u t 1 2 3 4 5 6 7 p e r i o d 1 1 s t p w m 2 u p d a t e p w m d u t y 3 2 n d p w m 4 u p d a t e p w m d u t y 0 x f f t c n c v a l u e 0 x 0 0 p w m n o u t p u t p e r i o d 5 3 t h p w m t c n c o v e r f l o w a n d t c n i r q s e t o l d t c n r o l d t c n r n e w t c n r n e w t c n r u p d a t e n e w t c n r ! o l d t c n r < t c n c < n e w t c n r u p d a t e n e w t c n r ! n e w t c n r < t c n c < o l d t c n r t c n c > = t c n r p w m h i g h > l o w t c n c < t c n r p w m l o w > h i g h
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 102 version 1.6 8.5.4 pwm program example ? example: setup pwm0 output from tc0 to pwm0out (p5. 3 ). the clock source is internal 12 mhz. fcpu = fosc/ 2 = 6mhz . the duty of pwm is 30/256. the pwm frequency is about 6khz. the pwm clock so urce is from external oscillator clock. tc 0 rate is fcpu/4. the tc 0 rate2~ tc 0 rate1 = 110. tc 0 c = tc 0 r = 30. mov a,#01100000b b0mov tc0 m,a ; set the tc0 rate to fcpu/4 mov a,#30 ; set the pwm duty to 30/256 b0mov tc0 c,a b0mov tc0 r,a b0bclr f tc0 out ; set duty range as 0/256~255/256. b0bclr faload0 b0bset fpwm0out ; enable pwm0 output to p5.4 and disable p5.4 i/o function b0bset f tc0 enb ; enable tc0 timer ? note: the tcn r is write - only register. dont process them using inc ms, decms instructions. ? example: modify tc0 r registers value. mov a, #30h ; input a number using b0mov instruction. b0mov tc 0 r, a incms buf0 ; get the new tc 0 r value from the buf0 buffer defined by nop ; programming. b0mov a, buf0 b0mov tc 0 r, a ? note: the pwm can work with interrupt request.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 103 version 1.6 9 universal serial bus (usb) 9.1 overview the usb is the answer to connectivity for the pc architecture. a fast, bi - directional interrupt pipe, low - cost, dynamically attachable serial interface is consistent with the requirements of the pc platform of today and tomorrow. the sonix usb microcontrollers are optimized for human - interface computer peripherals such as a mouse, keyboard, joystick, and game pa d. usb specif ication compliance conforms to usb specifications, version 2.0. supports 1 full - speed usb device address. supports 1 control endpoint, 2 interrupt endpoint s and 2 interrupt/bulk endpoints. integrated usb transceiver. 5v to 3.3v regulator output f or d+ 1.5k ohm internal resistor pull up. 9.2 usb machine the usb machine allows the microcontroller to communicate with the usb host. the hardware handles the following usb bus activity independently of the microcontroller. the usb machine will do: ? tra nslate the encoded received data and format the data to be transmitted on the bus. ? crc checking and generation by hardware. if crc is not correct, hardware will not send any response to usb host. ? send and update the data toggle bit (data1/0) automatica lly by hardware. ? send appropriate ack/nak/stall handshakes. ? setup, in, or out token type identification. set the appropriate bit once a valid token is received. ? place valid received data in the appropriate endpoint fifos. ? bit stuffing/unstuffing. ? address checking. ignore the transactions not addressed to the device. ? endpoint checking. check the endpoints request from usb host, and set the appropriate bit of registers. firmware is required to handle the rest of the following tasks: ? coordinate enumeration by decoding usb device requests. ? fill and empty the fifos. ? suspend/resume coordination. ? remote wake up function. ? determine the right interrupt request of usb communication.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 104 version 1.6 9.3 usb interrupt the usb function will accept the usb host c ommand and generate the relative interrupts, and the program counter will go to 0x08 vector. firmware is required to check the usb status bit to realize what request comes from the usb host. the usb function interrupt is generated when: ? the endpoint 0 is set to accept a setup token. ? the device receives an ack handshake after a successful read transaction (in) from the host. ? if the endpoint is in ack out modes, an interrupt is generated when data is received. ? the usb host send s usb suspend request to the device. ? usb bus reset event occurs. ? the usb endpoints interrupt after a usb transaction complete is on the bus. ? the sof packet received if the sof interrupt enable. ? the nak handshaking when the nak interrupt enable. the following examples show how to avoid the error of reading or writing the endpoint fifos and to do the right usb request routine according to the flag. 9.4 usb enumeration a typical usb enumeration sequence is shown below. 1. the host computer sends a setup packet followed by a d ata packet to usb address 0 requesting the device descriptor. 2. firmware decodes the request and retrieves its device descriptor from the program memory tables. 3. the host computer performs a control read sequence and firmware responds by sending the device de scriptor over the usb bus, via the on - chip fifo. 4. after receiving the descriptor, the host sends a setup packet followed by a data packet to address 0 assigning a new usb address to the device. 5. firmware stores the new address in its usb device address regis ter after the no - data control sequence completes. 6. the host sends a request for the device descriptor using the new usb address. 7. firmware decodes the request and retrieves the device descriptor from program memory tables. 8. the host performs a control read se quence and firmware responds by sending its device descriptor over the usb bus. 9. the host generates control reads from the device to request the configuration and report descriptors. 10. once the device receives a set configuration request, its functions may no w be used. 11. firmware should take appropriate action for endpoint 0 ~ 3 transactions, which may occur from this point.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 105 version 1.6 9.5 usb registers 9.5.1 usb device address register the usb device address register (uda) contains a 7 - bit usb device address and one bit t o enable the usb function. this register is cleared during a reset, setting the usb device address to zero and disable the usb function. 09 1 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 uda ude uda6 uda5 uda4 uda3 uda2 uda1 uda0 read/write r/w r/w r /w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 ude: device function enable. this bit must be enabled by firmware to enable the usb device function. 0 = disable usb device function. 1 = enable usb device function. bit [6:0] uda [6:0]: th ese bits must be set by firmware during the usb enumeration process (i.e., setaddress) to the non - zero address assigned by the usb host. 9.5.2 usb status register the usb status register indicates the status of usb. 0 9 2 h bit 7 bit 6 bit 5 bit 4 bit 3 bi t 2 bit 1 bit 0 ustatus crcerr pkterr sof bus_rst suspend ep0setup ep0in ep0out read/write r/w r/w r/w r r r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 crcerr: usb data crc check error. 0 = non - usb data crc check error, clear ed by firmware. 1 = set to 1 by hardware when usb data crc check error occur. bit 6 pkterr: usb packet error. 0 = non - usb packet error, clear ed by firmware. 1 = set to 1 by hardware when usb packet error occur. bit 5 sof: indicate the usb sies sof packet is received 0 = non usb sies sof packet received. 1 = if sof_int_en = 1 then this bit will be set to 1 by hardware when the sof packet is received. otherwise the bit will always be 0. bit 4 bus_rst: usb bus reset. 0 = non - usb bus reset. 1 = set to 1 by har dware when usb bus reset request.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 106 version 1.6 bit 3 suspend: indicate usb suspend status. 0 = non - suspend status. when mcu wakeup from sleep mode by usb resume wakeup request, the bit will changes from 1 to 0 automatically. 1 = set to 1 by hardware when usb susp end request. bit 2 ep0setup : endpoint 0 setup token received. 0 = endpoint 0 has no setup token received. 1 = a valid setup packet has been received. the bit is set to 1 after the last received packet in an setup transaction. while the bit is set to 1 , the host can not write any data in to ep0 fifo. this prevents sie from overwriting an incoming setup transaction before firmware has a chance to read the setup data. bit 1 ep0in : endpoint 0 in token received. 0 = endpoint 0 has no in token received. 1 = a valid in packet has been received. the bit is set to 1 after the last received packet in an in transaction. bit 0 ep0out : endpoint 0 out token received. 0 = endpoint 0 has no out token received. 1 = a valid out packet has been received. the bit is set to 1 after the last received packet in an out transaction. 9.5.3 usb data count register the usb ep0 out token data byte counter. 0 9 3 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ep0out_cnt uep0oc4 uep0oc3 uep0oc2 uep0oc1 uep0oc0 read/wr ite r/w r/w r/w r/w r/w after reset 0 0 0 0 0 bit [4:0] uep0c [4:0]: usb endpoint 0 out token data counter. 9.5.4 usb enable control register the register control the regulator output 3.3 volts enable, sof packet receive interrupt, nak handshaki ng interrupt and d+ internal 1.5k ohm pull up. 09 4 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 usb_int_en reg_en dp_up_en sof_int_en ep4nak _int_en ep3nak _int_en ep2nak _int_en ep1nak _int_en read/write r/w r/w r/w r/w r/w r/w r/w after reset 1 0 0 0 0 0 0 bit 7 reg_en: 3.3volts regulator control bit. 0 = disable regulator output 3.3volts.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 107 version 1.6 1 = enable regulator output 3.3volts. bit 6 dp_up_en: d+ internal 1.5k ohm pull up resistor control bit. 0 = disable d+ pull up 1.5k ohm to 3.3volts. 1 = enable d+ pull up 1.5k ohm to 3.3volts. bit 5 sof_int_en: usb sies sof packet receive interrupt enable. 0 = disable usb sies sof interrupt request. 1 = enable usb sies sof interrupt request. bit [ 3 :0] ep n nak_int_en [ 3 :0]: ep1~ep 4 nak transaction in terrupts enable control bits . n = 1, 2, 3 , 4 . 0 = disable nak transaction interrupt request. 1 = enable nak transaction interrupt request. 9.5.5 usb endpoint s ack handshaking flag register the status of endpoints ack transaction. 09 5 h bit 7 bit 6 b it 5 bit 4 bit 3 bit 2 bit 1 bit 0 ep_ack ep4_ack ep3_ack ep2_ack ep1_ack read/write r/w r/w r/w r/w after reset 0 0 0 0 bit [ 3 :0] ep n _ack [ 3 :0]: ep1 ~ep 4 a ck transaction . n= 1, 2, 3 , 4 . the bit is set whenever the endpoint that completes with an ack received. 0 = the endpoint (interrupt pipe) doesnt complete with an ack. 1 = the endpoint (interrupt pipe) complete with an ack . 9.5.6 usb endpoints nak handshaking flag register the status of endpoints nak transaction. 09 6 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ep_nak ep4_nak ep3_nak ep2_nak ep1_nak read/write r/w r/w r/w r/w after reset 0 0 0 0 bit [ 3 :0] epn _nak [ 3 :0]: ep1~ep 4 nak transaction . n = 1, 2, 3 , 4 . the bit is set whenever the endpoint that comple tes with an nak received. 0 = the ep n nak_int_en = 0 or the endpoint (interrupt pipe) doesnt complete with an nak. 1 = the epn nak_int_en = 1 and the endpoint (interrupt pipe) complete with an nak.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 108 version 1.6 9.5.7 usb endpoint 0 enable register an endpoint 0 (ep 0) is used to initialize and control the usb device. ep0 is bi - directional (control pipe), as the device, can both receive and transmit data, which provides to access the device configuration information and allows generic usb status and control accesses. 09 7 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ue0r - ue0m1 ue0m0 - ue0c3 ue0c 2 ue0c1 ue0c0 read/write - r/w r/w - r/w r/w r/w r/w after reset - 0 0 - 0 0 0 0 bit [6:5] ue0m [1:0]: the endpoint 0 modes determine how the sie responds to usb traf fic that the host sends to the endpoint 0. for example, if the endpoint 0s mode bit is set to 00 that is nak in/out mode as shown in table, the usb sie will send nak handshakes in response to any in/out token set to the endpoint 0.the bit 5 ue0m0 will aut o reset to zero when the ack transaction complete. usb endpoint 0s mode table ue0m1 ue0m0 in/out token handshake 0 0 nak 0 1 ack 1 0 stall 1 1 stall bit [3:0] ue0c [3:0]: indicate the number of data bytes in a transaction: for in transactions, f irmware loads the count with the number of bytes to be transmitted to the host from the endpoint 0 fifo. 9.5. 8 usb endpoint 1 enable register the communication with the usb host using endpoint 1, endpoint 1s fifo is implemented as w bytes of dedicated ra m. the endponit1 is an interrupt endpoint. 0 9 8 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ue1r ue1e ue1m1 ue1m0 read/write r/w r /w r/w after reset 0 0 0 bit 7 ue1e: usb endpoint 1 function enable bit. 0 = disable usb endpoint 1 function. 1 = enable usb endpoint 1 function. bit [6:5] ue1m [1:0]: the endpoint 1 modes determine how the sie responds to usb traffic that the host sends to the endpoint 1. for example, if the endpoint 1s mode bit is set to 00 that is nak in/out mode as shown in table, the usb sie will send nak handshakes in response to any in/out token set to the endpoint 1. the bit 5 ue1m0 will auto reset to zero when the ack transaction complete.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 109 version 1.6 usb endpoint 1s mode table ue1m1 ue1m0 in/out token handshake 0 0 n ak 0 1 ack 1 0 stall 1 1 stall 099h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ue1r_c ue1c5 ue1c4 ue1c3 ue1c ue1c1 ue1c0 read/write r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 bit [5:0] ue1c [5:0]: indicate the number of data byte s in a transaction: for in transactions, firmware loads the count with the number of bytes to be transmitted to the host from the endpoint 1 fifo. 9.5. 9 usb endpoint 2 enable register the communication with the usb host using endpoint 2, endpoint 2s fifo is implemented as x bytes of dedicated ram. the endpoint 2 is an interrupt endpoint. 0 9 a h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ue2r ue2e ue2m1 ue2m0 read/write r/w r /w r/w after reset 0 0 0 bit 7 ue2e: usb endpoint 2 funct ion enable bit. 0 = disable usb endpoint 2 function. 1 = enable usb endpoint 2 function. bit [6:5] ue2m [1:0]: the endpoint 2 modes determine how the sie responds to usb traffic that the host sends to the endpoint 2. for example, if the endpoint 2s mod e bit is set to 00 that is nak in/out mode as shown in table, the usb sie will send nak handshakes in response to any in/out token set to the endpoint 2. the bit 5 ue2m0 will auto reset to zero when the ack transaction complete. usb endpoint 2s mode tab le ue2m1 ue2m0 in/out token handshake 0 0 nak 0 1 ack 1 0 stall 1 1 stall
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 110 version 1.6 09bh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ue2r_c ue2c5 ue2c4 ue2c3 ue2c ue2c1 ue2c0 read/write r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 bit [5:0] ue2c [5:0]: indicate the number of data bytes in a transaction: for in transactions, firmware loads the count with the number of bytes to be transmitted to the host from the endpoint 2 fifo. 9.5.10 usb endpoint 3 enable register the communication with t he usb host using endpoint 3, endpoint 3s fifo is implemented as y bytes of dedicated ram. the endpoint 3 is an interrupt and bulk endpoint. 09 c h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ue3r ue3e ue3m1 ue3m0 read/write r/w r /w r/w af ter reset 0 0 0 bit 7 ue3e: usb endpoint 3 function enable bit. 0 = disable usb endpoint 3 function. 1 = enable usb endpoint 3 function. bit [6:5] ue3m [1:0]: the endpoint 3 modes determine how the sie responds to usb traffic that the host sends to the endpoint 3. for example, if the endpoint 3s mode bit is set to 00 that is nak in/out mode as shown in table, the usb sie will send nak handshakes in response to any in/out token set to the endpoint 3. the bit 5 ue3m0 will auto reset to zero when t he ack transaction complete. usb endpoint 3s mode table ue3m1 ue3m0 in/out token handshake 0 0 nak 0 1 ack 1 0 stall 1 1 stall 09dh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ue3r_c ue3c5 ue3c4 ue3c3 ue3c ue3c1 ue3c0 read/write r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 bit [5:0] ue3c [5:0]: indicate the number of data bytes in a transaction: for in transactions, firmware loads the count with the number of bytes to be transmitted to the host from the endpoint 3 fifo.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 111 version 1.6 9.5.11 usb endpoint 4 enable register the communication with the usb host using endpoint 4, endpoint 4s fifo is implemented as z bytes of dedicated ram. the endpoint 4 is an interrupt and bulk endpoint. 09eh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ue4r ue4e ue4m1 ue4m0 read/write r/w r/w r/w after reset 0 0 0 bit 7 ue4e: usb endpoint 4 function enable bit. 0 = disable usb endpoint 4 function. 1 = enable usb endpoint 4 function. bit [6:5] ue4m [1:0]: the endpoint 4 modes determine how the sie responds to usb traffic that the host sends to the endpoint 4. for example, if the endpoint 4s mode bit is set to 00 that is nak in/out mode as shown in table, the usb sie will send nak handshakes in response to any in/out token set to the end point 4. the bit 5 ue4m0 will auto reset to zero when the ack transaction complete. usb endpoint 4s mode table ue4m1 ue4m0 in/out token handshake 0 0 nak 0 1 ack 1 0 stall 1 1 stall 09fh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ue4r_c u e4c5 ue4c4 ue4c3 ue4c ue4c1 ue4c0 read/write r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 bit [5:0] ue4c [5:0]: indicate the number of data bytes in a transaction: for in transactions, firmware loads the count with the number of bytes to be tra nsmitted to the host from the endpoint 4 fifo. 9.5.12 usb endpoint fifo address setting register 0a0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ep2fifo_a ddr ep2fifo7 ep2fifo6 ep2fifo5 ep2fifo4 ep2fifo3 ep2fifo2 ep2fifo1 ep2fifo0 read/write r/w r /w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit [7:0] ep2fifo_addr [7:0]: ep2 fifo start address.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 112 version 1.6 0a1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ep3fifo_a ddr ep3fifo7 ep3fifo6 ep3fifo5 ep3fifo4 ep3fifo3 ep3fifo2 ep3fifo1 ep3fifo0 rea d/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit [7:0] ep3fifo_addr [7:0]: ep3 fifo start address. 0a2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ep4fifo_a ddr ep4fifo7 ep4fifo6 ep4fifo5 ep4fifo4 ep4fifo3 ep4fifo2 ep4fifo1 ep4fifo0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit [7:0] ep4fifo_addr [7:0]: ep4 fifo start address. 9.5. 1 3 usb data pointer register usb fifo address pointer. use the point to set the fifo address for reading data fro m usb fifo and writing data to usb fifo. 0a 3 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 u dp0 udp07 udp06 udp05 udp04 udp03 udp02 udp01 udp00 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 usb data pointer: access the usb data by the data pointer. 9.5. 1 4 usb data read/write register 0a 5 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 udr0 _r udr0 _r 7 udr0_r 6 udr0_r 5 udr0_r 4 udr0_r 3 udr0_r 2 udr0_r 1 udr0_r 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 udr0 _r: read the data from usb fifo which udp0 register point to. 0a6h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 udr0_w udr0_w 7 udr0_w 6 udr0_w 5 udr0_w 4 udr0_w 3 udr0_w 2 udr0_w 1 udr0_w 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 udr0_w: write the data to usb fifo which udp0 register point to. 9.5.1 5 upid register forcing bits allow firmware to directly drive the d+ and d C pins. 0a 7 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 upid - - - - ubde ddp ddn read/write - - - - r/ w r/ w r/ w after reset - - - - 0 0 0
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 113 version 1.6 bit 2 ubde: enable to direct drive usb bus. 0 = disable. 1 = enable. bit 1 ddp: drive d+ on the usb bus. 0 = drive d+ low. 1 = drive d+ high. bit 0 ddn: drive d - on the usb bus . 0 = drive d - low. 1 = drive d - high. 9.5.1 6 endpoint toggle bit control register . 0ach bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 utoggle - - - - ep4 _data01 ep3 _data01 ep2 _data01 ep1 _data01 read/write - - - - r/w r/w r/w r/w after res et - - - - 1 1 1 1 bit [ 3 :0] endpoint 1~ 4 s data0/1 toggle bit control. 0 = clear the endpoint 1~ 4 s toggle bit to data0 1 = hardware set toggle bit automatically.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 114 version 1.6 10 universal asynchronous receiver/transmitter (uart) 10.1 overview t he uart interface is an universal asynchronous receiver/transmitter method. the serial interface is applied to low speed data transfer and communicate with low speed peripheral devices. the uart transceiver of sonix 8 - bit mcu allows rs232 standard and supp orts one and two bytes data length. the transfer format has start bit, 8/16 - bit data, parity bit and stop bit. programmable baud rate supports different speed peripheral devices. uart i/o pins support push - pull and open - drain structures controlled by regis ter. the uart features include the following: ? full - duplex, 2 - wire asynchronous data transfer. ? programmable baud rate. ? 8 - bit and 16 - bit data length. ? odd and even parity bit. ? end - of - transfer interrupt. 10.2 uart operation the uart rx and tx pins are shar ed with gpio. when uart enables (urxen=1, utxen=1), the uart shared pins transfers to uart purpose and disable gpio function automatically. when uart disables, the uart pins returns to gpio last status. the uart data buffer length supports 1 - byte and 2 - byt e. after uart rx operation finished, the utrxirq sets as D1. after uart tx operation finished, the uttxirq sets as D1. the uart irq bits are cleared by program. if the utrxien or uttxien set to enable, the utrxirq and uttxirq triggers the interrupt reque st and program counter jumps to interrupt vector to execute interrupt service routine. uart interface circuit diagram f h o s c u a r t b a u d r a t e c o n t r o l b l o c k ( p r e - s c a l e r a n d d i v i d e r ) u r r x d 1 8 - b i t b u f f e r u r x u r x e n c p u m 1 , 0 u a r t i / o c o u n t e r p a r i t y c h e c k u r r x d 2 8 - b i t b u f f e r u r x m u r x p s u r x p e n u r x s 1 , 0 a n d r x i n t e r r u p t t x i n t e r r u p t u r x e n u r x p c u r t x d 1 8 - b i t b u f f e r u t x u t x e n c p u m 1 , 0 p a r i t y c h e c k u r t x d 2 8 - b i t b u f f e r u t x m u t x p s u t x p e n u t x p c u t x e n
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 115 version 1.6 the uart transfer format includes Dbus idle status, Dstart bit, D8 - bit data, Dparity bit and Dstop bit as following. uart transfer format with parity bit uart transfer format without parity bit bus idle status the bus idle status is the bus non - operating status. the uart receiver bus idle stat us of mcu is floating status and tied high by the transmitter device terminal. the uart transmitter bus idle status of mcu is high status. the uart bus will be set when urxen and utxen are enabled. start bit uart is a asynchronous type of communication a nd need a attention bit to offer receiver the transfer starting. the start bit is a simple format which is high to low edge change and the duration is one bit period. the start bit is easily recognized by the receiver. 8 - bit data the data format is 8 - bit length, and lsb transfers first following start bit. the one bit data duration is the unit of uart baud rate controlled by register. parity bit the parity bit purpose is to detect data error condition. it is an extra bit following the data stream. the pa rity bit includes odd and even check methods controlled by urxps/utxps bits. after receiving data and parity bit, the parity check executes automatically. the urxpc bit indicates the parity check result. the parity bit function is controlled by urxpen/utxp en bits. if the parity bit function is disabled, the uart transfer contents remove the parity bit and the stop bit follows the data stream directly. stop bit the stop bit is like start bit using a simple format to indicate the end of uart transfer. the st op bit format is low to high edge change and the duration is one bit period. b i t 0 b i t 1 b i t 2 b i t 3 b i t 4 b i t 5 b i t 6 s t a r t b i t 7 p a r i t y s t o p i d l e s t a t u s i d l e s t a t u s s t a r t s t o p i d l e s t a t u s i d l e s t a t u s b i t 0 b i t 1 b i t 2 b i t 3 b i t 4 b i t 5 b i t 6 b i t 7
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 116 version 1.6 the uart communication supports 2 - byte data length. the function is for continuous data streams and immediate data request. the 2 - byte data format is a continuously byte data fo rm. the gap between the 2 - byte data is unit baud rate. the first byte data stores in urrxd1 (receiver) and urtxd1 (transmitter). the second byte data stores in urrxd2 (receiver) and urtxd2 (transmitter).the 2 - byte data format is as following. 2 - byte transfer format with parity bit 2 - byte transfer format without parity bit the uart supports interrupt function. utrxien/uttxien are uart transfer interrupt function control bit. utrxien=0, disable u art receiver interrupt function. uttxien=0, disable uart transmitter interrupt function. utrxien=1, enable uart receiver interrupt function. uttxien=1, enable uart transmitter interrupt function. when uart interrupt function enable, the program counter poi nts to interrupt vector (org 8) to do uart interrupt service routine after uart operating. utrxirq and uttxirq are uart interrupt request flags, and also to be the uart operating status indicator when utrxien=0 or uttxien=0, but cleared by program. when ua rt operation finished, the utrxirq/uttxirq would be set to D1. note: the first step of uart operation is to setup the uart pins mode. enable urxen/utxen to control uart pins mode. b i t 0 s t a r t b i t 7 p a r i t y s t o p i d l e s t a t u s . . . b i t 0 s t a r t b i t 7 p a r i t y s t o p . . . g a p i d l e s t a t u s i d l e s t a t u s t h e f i r s t d a t a b y t e ( l o w b y t e ) t h e s e c o n d d a t a b y t e ( h i g h b y t e ) b i t 0 s t a r t b i t 7 s t o p i d l e s t a t u s . . . b i t 0 s t a r t b i t 7 s t o p . . . g a p i d l e s t a t u s i d l e s t a t u s t h e f i r s t d a t a b y t e ( l o w b y t e ) t h e s e c o n d d a t a b y t e ( h i g h b y t e )
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 117 version 1.6 10.3 uart transmitter control register urtx ini tial value = 0 xx0000x 0a9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 urtx uclks utxen utxpen utxps utxm read/write r/w r/w r/w r/w r/w after reset 0 0 0 0 0 bit 7 uclks: uart clock source select bit. 0 = uart clock source is 16mhz. 1 = uart clock source is 24mh z . bit 4 utxen: uart tx control bit. 0 = disable uart tx. utx pin keeps and returns to gpio function. 1 = enable uart tx. utx pin transmits uart data. bit 3 utxpen: uart tx parity bit check function control bit. 0 = disab le uart tx parity bit check function. the data stream doesnt include parity bit. 1 = enable uart tx parity bit check function. the data stream includes parity bit. bit 2 utxps: uart tx parity bit format control bit. 0 = uart tx parity bit format is ev en parity. 1= uart tx parity bit format is odd parity. bit 1 utxm: uart tx data buffer length control bit. 0 = 1 - byte. 1 = 2 - byte.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 118 version 1.6 10.4 uart receiver control register urrx initial value = 000 0000x 0a a h bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 urrx urxen urxs1 urxs0 urxpen urxps urxpc urxm r ead /w rite r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 bit 7 urxen: uart rx control bit. 0 = disable uart rx. urx pin keeps and returns to gpio function. 1 = ena ble uart rx. urx pin receives uart data. bit[6:5] urxs1, urxs0: uart rx status indicator. 00 = no data received. 01 = data received, but parity checking error occurrence. 10, 11 = data received successfully. bit 4 urxpen: uart rx parity bit check fu nction control bit. 0 = disable uart rx parity bit check function. the data stream doesnt include parity bit. 1 = enable uart rx parity bit check function. the data stream includes parity bit. bit 3 urxps: uart rx parity bit format control bit. 0 = ua rt rx parity bit format is even parity. 1= uart rx parity bit format is odd parity. bit 2 urxpc: uart rx parity bit checking status bit. 0 = uart rx parity bit checking is error. 1 = uart rx parity bit checking is correct. bit 1 urxm: uart rx data buffer length control bit. 0 = 1 - byte. 1 = 2 - byte.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 119 version 1.6 10.5 uart baud rate control register urbrc initial value =11010101 0a b h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 urbrc udiv4 udiv3 udiv2 udiv1 udiv0 upcs2 upcs1 upcs0 r ea d /w rite r/w r/w r/w r/w r/w r/w r/w r/w after reset 1 1 0 1 0 1 0 1 bit[7:3] udiv[4:0]: uart baud rate divider. bit[2:0] upcs[2:0]: uart baud rate pre - scalar. the uart baud rate clock source is fhosc and divided by pre - scalar and divider. the equatio n is as following. uart baud rate = ( fhosc / 2 p prescal a r p / (divider +1) ) / 16 divider ? baud rate uart clock source = 16mhz (uclks = 0) uart clock source = 24mhz (uclks = 1) upcs[2:0] udiv[4:0] upcs[2:0] udiv[4:0] 1200 101 11010 - - 2400 100 1 1010 - - 4800 011 11010 - - 9600 010 11010 - - 19200 001 1100 1 - - 38400 000 11001 - - 51200 000 10011 - - 57600 000 10000 - - 102400 000 01001 - - 115200 - - 000 01 1 00
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 120 version 1.6 10.6 uart data buffer urtxd1 initial value = 00000000 0a c h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 urtxd1 utxd17 utxd16 utxd15 utxd14 utxd13 utxd12 utxd11 utxd10 r ead /w rite r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit[7:0] urtxd1: uart transmitted data buffer byte 1. urtxd2 initial value = 00000000 0a d h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 urtxd2 utxd27 utxd26 utxd25 utxd24 utxd23 utxd22 utxd21 utxd20 r ead /w rite r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit[7:0] urtxd2: uart transmitted data buffer byte 2. urrxd1 initial value = 00000000 0a e h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 urrxd1 r ead /w rite r r r r r r r r after reset 0 0 0 0 0 0 0 0 bit[7:0] urrxd1: uart received data buffer byte 1. urrxd2 initial value = 00000000 0 a f h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 urrxd2 r ead /w rite r r r r r r r r after reset 0 0 0 0 0 0 0 0 bit[7:0] urrxd2: uart received data buffer byte 2. uart data mode urtxd2 urtxd1 urrxd2 urrxd1 1 - byte 0x00 1 - byte data 0x00 1 - b yte data 2 - byte high - byte data low - byte data high - byte data low - byte data
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 121 version 1.6 11 serial input/output transceiver 1 1 .1 overview the sio (serial input/output) transceiver allows high - speed synchronous data transfer between the sn8f 2280 series mcu and perip heral devices or between several sn8f 2280 devices. these peripheral devices may be serial eeproms, shift registers, display drivers, etc. the sn8f 2280 sio features include the following: ? full - duplex, 3 - wire synchronous data transfer ? tx/rx or tx only mode ? master (sck is clock output) or slave (sck is clock input) operation ? msb /lsb first data transfer ? s d o (p 2 . 1 ) is programmable open - drain output pin for multiple salve devices application ? two programmable bit rates (only in master mode) ? end - of - transfer interr upt the siom register can control sio operating function, such as: transmit/receive, clock rate, transfer edge and starting this circuit. this sio circuit will transmit or receive 8 - bit data automatically by setting senb and start bits in siom register. the siob is an 8 - bit buffer, which is designed to store transfer data. sioc and sior are designed to generate sios clock source with auto - reload function. the 3 - bit i/o counter can monitor the operation of sio and announce an interrupt request after trans mitting/receiving 8 - bit data. after transferring 8 - bit data, this circuit will be disabled automatically and re - transfer data by programming siom register. sio interface circuit diagram 1 f c p u c p u m 1 , 0 s e n b s c k s e n b s c l k m d s i o 8 - b i t c o u n t e r c p u m 1 , 0 s i o r r e g i s t e r a u t o - r e l o a d c p o l s i o 3 - b i t i / o c o u n t e r s i o t i m e o u t s i o b 8 - b i t b u f f e r 8 - b i t r e c e i v e b u f f e r m l s b s o s e n b c p u m 1 , 0 s i s e n b c p u m 1 , 0 m l s b c p h a s r a t e 1 , 0 s t a r t
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 122 version 1.6 the system is single - buffered in the transmit direction and double - buffered in the receive direction. this means that bytes to be transmitted cannot be written to the siob data register before the entire shift cycle is completed. when receiving data, however, a received byte must be read from the siob data register before the next byte has been completely shifted in. otherwise, the first byte is lost. following figure shows a typical sio transfer between two sn8f 2280 micro - controllers. master mcu sends sck for initial the data transfer. both m a s ter and slave mcu must work in the same clock edge direction, and then both controllers would send and receive data at the same time. sio data transfer diagram shift register (siob) 2nd receive buffer (address = siob) i n t e r n a l b u s read siob write siob sio master (sckmd = 0) so si sck shift register (siob) 2nd receive buffer (address = siob) i n t e r n a l b u s read siob write siob sio slave (sckmd = 1) si so sck
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 123 version 1.6 the sio data transfer timing as following figure: m l s b c p o l c p h a sck idle status diagrams 0 0 1 low 0 1 1 high 0 0 0 low 0 1 0 high 1 0 1 low 1 1 1 high 1 0 0 low 1 1 0 high sio data transfer timing b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 n e x t d a t a b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 n e x t d a t a b i t 0 b i t 1 b i t 2 b i t 3 b i t 4 b i t 5 b i t 6 b i t 7 b i t 0 b i t 1 b i t 2 b i t 3 b i t 4 b i t 5 b i t 6 b i t 7 n e x t d a t a b i t 0 b i t 1 b i t 2 b i t 3 b i t 4 b i t 5 b i t 6 b i t 7 n e x t d a t a b i t 0 b i t 1 b i t 2 b i t 3 b i t 4 b i t 5 b i t 6 b i t 7
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 124 version 1.6 1 1 .2 siom mode register 0b 0 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 siom senb start srate1 srate0 mlsb sckmd cpol cpha read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 senb: sio function control bit. 0 = d isable (p 2 .0~p 2 .2 is general purpose i/o port). 1 = e nable (p 2 .0~p 2 .2 is sio pins). bit 6 start: sio progress control bit. 0 = end of tr ansfer. 1 = p rogressing. bit [5:4] srate1: 0: sios transfer rate select bit. these 2 - bits are workless when sckmd=1. 00 = f cpu /2 . 01 = f cpu/ 64 10 = f cpu/ 32 11 = f cpu/ 16 . bit 3 mlsb: msb/lsb transfer first. 0 = msb transmit first. 1 = lsb transmit first. bit 2 sckmd: sios clock mode select bit. 0 = internal. (master mode) 1 = external. (slave mode) bit 1 cpol : sios transfer clock edge select bit. 0 = sck idle status is low status 1 = sck idle status is high status bit 0 cpha : the clock phase bit contr ols the phase of the clock on which data is sampled. 0 = data receive at the fisrt clock phase. 1 = data receive at the second clock phase. ? note: 1. if sckmd=1 for external clock, the sio is in slave mode. if sckmd=0 for internal clock, the sio is in master mode. 2. dont set senb and start bits in the same time. that makes the sio function error. because sio function is shared with port 2 for p 2 .0 as sck, p 2 .1 as s d o and p 2 .2 as s d i . the following table shown the port 2 [2:0] i/o mode behavior and setting when sio function enable and disable. senb=1 (sio function enable) p 2 .0/sck (sckmd=1) sio source = external clock p 2 .0 will change to input mode automatically, no matter what p 2 m setting (sckmd=0) sio source = internal clock p 2 .0 will chang e to output mode automatically, no matter what p 2 m setting p 2 .1/sd o sio = transmitter/receiver p 2 . 1 will change to output mode automatically, no matter what p 2 m setting p 2 .2/sd i p 2 . 2 must be set as input mode in p 2 m ,or the sio function will be abnormal senb=0 (sio function disable) p 2 .0/p 2 .1/p 2 .2 port 2 [2:0] i/o mode are fully controlled by p 2 m when sio function is d isable
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 125 version 1.6 1 1 .3 siob data buffer 0b 2 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 siob siob7 siob6 siob5 siob4 siob3 siob2 siob1 siob0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 siob is the sio data buffer register. it stores serial i/o transmit and receive data. 1 1 .4 sior register description 0b 1 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sior sior7 sior6 sior5 sior4 sior3 sior2 sior1 sior0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 the sior is designed for the sio counter to reload the counted value when end of counting. it is like a post - scaler of sio clock source and let sio has more flexible to setting sck range. users can set the sior value to setup sio transfer time. to setup sior value equation to desire transfer time is as following. sck frequency = sio rate / (256 - sior) ; sior = 256 - ( 1 / ( sck frequency ) * si o rate ) exam ple: setup the sio clock to be 2mhz. fosc = 12 mhz. sios rate = fcpu /2 . fcpu = fosc/1 = 12mhz. sior = 256 C (1/( 2mhz) * 12mhz/ 2 ) = 256 C 3 = 253 = 0xfd
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 126 version 1.6 example: master, duplex transfer and transmit data on rising edge mov a,txdata ; load transmitted data into siob register. b0mov siob,a mov a,#0f e h ; set sio clock b0mov sior,a mov a,#10 000000 b ; setup siom and enable sio function. b0mov siom,a b0bset fstart ; start transfer and receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a example: slave, duplex transfer and transmit data on rising edge mov a,txdata ; load transfer data into siob register. b0mov s iob,a mov a,# 10 000100 b ; setup siom and enable sio function. b0mov siom,a b0bset fstart ; start transfer and receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxda ta buffer. mov rxdata,a
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 127 version 1.6 12 8 channel analog to digital converter 1 2 .1 overview the analog to digital converter (adc) is sar structure with 8 - input sources and up to 4096 - step resolution t o transfer analog signal into 12 - bits digital data. use chs[2:0] bits to select analog signal input pin (ain pin), and gchs bit enables global adc channel, the analog signal inputs to the sar adc. the adc resolution can be selected 8 - bit and 12 - bit resolut ions through adlen bit. the adc converting rate can be selected by adcks[1:0] bits to decide adc converting time. the adc also builds in p4con register to set pure analog input pin. it is necessary to set p4 as input mode with pull - up resistor by program. after setup adenb and ads bits, the adc starts to convert analog signal to digital data. when the conversion is complete, the adc circuit will set eoc and adcirq bits to D1 and the digital data outputs in adb and adr registers. if the adcien = 1, the adc interrupt request occurs and executes interrupt service routine when adcirq = 1 after adc converting. ? note: 1. set adc input pin i/o direction as input mode without pull - up resistor. 2. disable adc (set adenb = 0) before enter power down (sleep) mod e to save power consumption. 3. set related bit of p4con register to avoid extra power consumption in power down mode. 4. delay 100us after enable adc (set adenb = 1) to wait adc circuit ready for conversion. a i n 5 a i n 4 a i n 7 a i n 6 a i n 3 a i n 2 a i n 1 a i n 0 p 4 c o n c h s [ 3 : 0 ] g c h s i n t e r n a l v d d a d c h i g h r e f e r e n c e v o l t a g e a n a l o g i n p u t a d e n b a d s a d c c l o c k c o u n t e r a d c k s [ 1 : 0 ] a d l e n a d b [ 1 1 : 0 ] e o c a d c i r q 8 / 1 2 s a r a d c v s s i n t e r n a l v d d
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 128 version 1.6 1 2 .2 adm register 0b6h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adm adenb ads eoc gchs chs3 chs2 chs1 chs0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 adenb: adc control bit. 0 = disable. 1 = enable. bit 6 ads: adc start control bit . 0 = adc conver ting stops. 1 = start to execute adc converting. bit 5 eoc: adc status bit. 0 = adc progressing. 1 = end of converting and reset ads bit. bit 4 gchs: adc global channel select bit. 0 = disable ain channel. 1 = enable ain channel. bit [ 3 :0] chs[ 3 :0] : adc input channel select bit. 0 000 = ain0 . 0 001 = ain1 . 0 010 = ain2 . 0 011 = ain3 . 0 100 = ain4 . 0 101 = ain5 . 0 110 = ain6 . 0 111 = ain7 . 1000 = vss. 1001 = vdd . 1 2 .3 adr registers 0b8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adr adcks 2 a dcks1 adcks0 adlen adb3 adb2 adb1 adb0 read/write r/w r/w r/w r/w r r r r after reset 0 0 0 0 - - - - bit [7:5] adcks [ 2 :0]: adcs clock source select bit. adcks 2 adcks 1 adcks0 adc clock source 0 0 0 fcpu/16 0 0 1 fcpu/8 0 1 0 fcpu/1 0 1 1 fcpu/2 1 0 0 fcpu/64 1 0 1 fcpu/32 1 1 0 fcpu/4 1 1 1 reserved bit 4 adlen: adcs resolution select bits. 0 = 8 - bit. 1 = 12 - bit. bit [3:0] adb [3:0]: 12 - bit low - nibble adc data buffer.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 129 version 1.6 1 2 .4 adb registers 0b7h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adb adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 read/write r r r r r r r r after reset - - - - - - - - bit[7:0] adb[7:0]: 8 - bit adc data buffer and the high - byte data buffer of 12 - bit adc. adb is adc data buffer to store adc converter result. the adb register is only 8 - bit register including bit 4~bit11 adc data. to combine adb register and the low - nibble of adr will get full 12 - bit adc data buffer. the adc buffer is a read - only register and the initial status is unknown after system reset. ? adb[11:4]: in 8 - bit adc mode, the adc data is stored in adb register. ? adb[11:0]: in 12 - bit adc mode, the adc data is stored in adb and adr registers. ? note: the initial status of adc data buffer including adb register and adr low - nibble after the system reset is unknown. the ains input voltage v.s. adbs output data ain n adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 adb3 adb2 adb1 adb0 0/4096*vrefh 0 0 0 0 0 0 0 0 0 0 0 0 1/4096*vrefh 0 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4094/4096*vrefh 1 1 1 1 1 1 1 1 1 1 1 0 4095/4096*vrefh 1 1 1 1 1 1 1 1 1 1 1 1 for different applications, users maybe need more than 8 - bit resolution but less than 12 - bit. to process the adb and adr data can ma ke the job well. first, the ad resolution must be set 12 - bit mode and then to execute adc converter routine. then delete the lsb of adc data and get the new resolution result. the table is as following. adc resolution adb adr adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 adb3 adb2 adb1 adb0 8 - bit o o o o o o o o x x x x 9 - bit o o o o o o o o o x x x 10 - bit o o o o o o o o o o x x 11 - bit o o o o o o o o o o o x 12 - bit o o o o o o o o o o o o o = selected, x = delete
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 130 version 1.6 1 2 .5 p4con registers the port 4 is shared with adc input function. only one pin of port 4 can be configured as adc input in the same time by adm register. the other pins of port 4 are digital i/o pins. connect an analog signal to coms digital input pin, especially, the analog sig nal level is about 1/2 vdd will cause extra current leakage. in the power down mode, the above leakage current will be a big problem. unfortunately, if users connect more than one analog input signal to port 4 will encounter above current leakage situation . p4con is port4 configuration register. write D1 into p4con [7:0] will configure related port 4 pin as pure analog input pin to avoid current leakage. 0b9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4con p4con7 p4con6 p4con5 p4con4 p4con3 p4con 2 p4con1 p4con0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 bit[4:0] p4con[7:0]: p4.n configuration control bits. 0 = p4.n can be an analog input (adc input) or digital i/o pins. 1 = p4.n is pure analog input, cant be a digital i/o pin . ? note: when port 4.n is general i/o port not adc channel, p4con.n must set to 0 or the port 4.n digital i/o signal would be isolated. 1 2 .6 adc converting time the adc converting time is from ads=1 (start to adc convert) to eoc=1 (end of adc conv ert). the converting time duration is depend on adc resolution. 12 - bit adcs converting time is 1/(adc clock /4)*16 sec, and the 8 - bit adc converting time is 1/(adc clock /4)*12 sec. the adc converting time affects adc performance. if input high rate analo g signal, it is necessary to select a high adc converting rate. if the adc converting time is slower than analog signal variation rate, the adc result would be error. so to select a correct adc clock rate and adc resolution to decide a right adc converting rate is very important. 12 - bit adc conversion time = 1/(adc clock /4)*16 sec 8 - bit adc conversion time = 1/(adc clock /4)*12 sec fcpu = 4mhz ( high clock oscillator frequency (fosc) is 16mhz and fcpu = fosc/4) adlen adcks1 adcks0 adc clock a dc conversion time 0 (8 - bit) 0 0 fcpu/16 1/(4mhz/16/4)*12 = 192 us 0 1 fcpu/8 1/(4mhz/8/4)*12 = 96 us 1 0 fcpu 1/(4mhz/4)*12 = 12 us 1 1 fcpu/2 1/(4mhz/2/4)*12 = 24 us 1 (12 - bit) 0 0 fcpu/16 1/(4mhz/16/4)*16 = 256 us 0 1 fcpu/8 1/(4mhz/8/4)*16 = 128 us 1 0 fcpu 1/(4mhz/4)*16 = 16 us 1 1 fcpu/2 1/(4mhz/2/4)*16 = 32 us
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 131 version 1.6 1 2 .7 adc contorl notice 1 2 .7.1 adc signal the adc high reference voltage is internal vdd. the adc low reference voltage is ground. the adc input signal voltage range must be from high reference vol tage to low reference voltage. 1 2 .7.2 adc program the first step of adc execution is to setup adc configuration. the adc program setup sequence and notices are as following. ? step 1: enable adc. adenb is adc control bit to contro l. adenb = 1 is to enable adc. adenb = 0 is to disable adc. when adenb is enabled, the system must be delay 100us to be the adc warm - up time by program, and then set ads to do adc converting. the 100us delay time is necessary after adenb setting (not ads s etting), or the adc converting result would be error. normally, the adenb is set one time when the system under normal run condition, and do the delay time only one time. ? step 2 : select the adc input pin by chs[2:0], enable p4cons related bit for the adc input pin, and enable adc global input. when one ain pin is selected to be analog signal input pin, it is necessary to setup the pin as input mode and disable the pull - up resistor by program. also to set the p4con, and the digital i/o function including p ull - up is isolated. ? step 3 : start to execute adc conversion by setting ads = 1. ? step 4 : wait the end of adc converting through checking eoc = 1 or adcirq = 1. if enable adc interrupt function, the program executes adc interrupt service when adc interrupt occurrence. ads is cleared when the end of adc converting automatically. eoc bit indicates adc processing status immediately and is cleared when ads = 1. users neednt to clear it by program. ? example : configure ain0 as 12 - bit adc input and start adc co nversion then enter power down mode. adc0: b0bset fadenb ; enable adc circuit call delay100us ; delay 100us to wait adc circuit ready for conversion mov a, #0feh b0mov p4ur, a ; disable p4.0 pull - up resistor b0bclr fp40m ; set p4.0 as input pin mov a, #01h b0mov p4con, a ; set p4.0 as pure analog input mov a, #60h b0mov adr, a ; to set 12 - bit adc and adc clock = fosc. mov a,#90h b0mov adm,a ; to enable adc and set ain0 input b0bset fads ; to start conversion wadc0: b0bt s1 feoc ; to skip, if end of converting =1 jmp wadc0 ; else, jump to wadc0 b0mov a,adb ; to get ain0 input data bit11 ~ bit4 b0mov adc_buf_hi, a b0mov a,adr ; to get ain0 input data bit3 ~ bit0 and a, 0fh b0mov adc_buf_low, a power_down . . b0bclr fadenb ; disable adc circuit b0bclr fcpum1 b0bset fcpum0 ; enter sleep mode
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 132 version 1.6 1 2 .8 adc circuit the analog signal is inputted to adc input pin Dainn/p4.n. the adc input signal must be through a 0.1uf ca pacitor Da. the 0.1uf capacitor is set between adc input pin and vss pin, and must be on the side of the adc input pin as possible. dont connect the capacitors ground pin to ground plain directly, and must be through vss pin. the capacitor can reduce th e power noise effective coupled with the analog signal. v c c g n d 0 . 1 u f a n a l o g s i g n a l i n p u t m a i n p o w e r t r u n k a i n n / p 4 . n v s s m c u a
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 133 version 1.6 13 main series port (msp) 13.1 overview the msp (main serial port) is a serial communication interface for data exchanging from one mcu to one mcu or other hardware perip herals. these peripheral devices may be serial eeprom, a/d converters, display device, etc. the msp module can operate in one of two modes : ? full master mode ? slave mode (with general address call) the msp features include the following: ? 2 - wire synchrono us data transfer / receiver. ? master (scl is clock output) or slave (scl is clock input) operation. ? scl, sda are programmable open - drain output pin for multiple salve devices application. ? support 400k clock rate @ fcpu=4mips. ? end - of - transfer/receiver int errupt. 13.2 msp status register mspstat initial value =x00000x0 0eah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mspstat cke d _ a p s red _ wrt bf read/write r/w r r r r r after reset 0 0 0 0 0 0 bit 6 cke: slave clock edge control bit . in slave mode: receive address or data byte . 0 = latch data on scl rising edge. (default) 1 = latch data on scl falling edge. ? note 1. in slave transmit mode, address received depended on cke setting. data transfer on scl falling edge. ? note 2. in slave rece iver mode, address and data received depended on cke setting. bit 5 d _ a : data/address bit . 0 = indicates the last byte received or transmitted was address. 1 = indicates the last byte received or transmitted was data. bit 4 p: stop bit . 0 = stop bit w as not detected. 1 = indicates that a stop bit has been detected last. ? note1. it will be cleared when start bit was detected. bit 3 s: start bit. 0 = start bit was not detected. 1 = indicates that a start bit has been detected last . ? note1. it will be cleared when stop bit was detected. bit 2 red _ wrt: read/write bit information . this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 134 version 1.6 the next start bit, stop bit, or not ack bit. in s lave mode : 0 = write . 1 = read . in master mode : 0 = transmit is not in progress. 1 = transmit is in progress . or this bit with sen, rsen, pen, rcen, or acken will indicate if the msp is in idle mode. bit 0 bf: buffer full status bit . receive : 1 = recei ve complete, mspbuf is full . 0 = receive not complete, mspbuf is empty . transmit : 1 = data transmit in progress (does not include the ack and stop bits), mspbuf is full . 0 = data transmit complete (does not include the ack and stop bits), mspbuf is empty . 13.3 msp mode register 1 msp m1 initial value = 0 00000x0 0ebh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mspm1 wcol mspov mspenb ckp slrxckp mspwk mspc read/write r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 bit 7 wcol : write collisi on detect bit . master mode : 0 = no collision . 1 = a write to the mspbuf register was attempted while the msp conditions were not valid for a transmission to be started . slave mode : 0 = no collision . 1 = the mspbuf register is written while it is still tra nsmitting the previous word . (must be cleared in software) bit 6 mspov: receive overflow indicator bit . 0 = no overflow. 1 = a byte is received while the mspbuf register is still holding the previous byte. mspov is a Ddont care in transmit mode. mspov must be cleared in software in either mode. (must be cleared in software) bit 5 mspenb: main serial port communication enable . 0 = disables main serial port and configures these pins as i/o port pins. 1 = enables main serial port and configures scl and s da as the source of the serial port pins. bit 4 ckp: scl clock priority control bit . in msp slave mode : 0 = hold scl keeping low. (ensure data setup time and slave device ready) 1 = release scl clock. (slave transistor mode ckp function always enables, slave receiver ckp function control by slrxckp) in msp master mode : unused. bit 3 slrxckp: slave receiver mode scl clock priority control bit . in msp slave receiver mode :
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 135 version 1.6 0 = dis able ckp function. 1 = en able ckp function. in msp master and slave transis tor mode : unused. bit 2 mspwk: msp wake - up indication bit . 0 = mcu not wake - up by msp. 1 = mcu wake - up by msp. ? note : clear mspwk before entering power down mode for indication the wake - up source from msp or not. bit 0 mspc: msp mode control register . 0 = msp operated on slave mode, 7 - bit address. 1 = msp operated on master mode. 13.4 msp mode register 2 msp m2 initial value = 0 00000 0 0 0ech bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mspm2 gcen ackstat ackdt acken rcen pen rsen sen read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 gcen: general call enable bit . (in slave mode only) 0 = general call address disabled . 1 = enable interrupt when a general call address (0000h) is received. bit 6 ackstat: acknowledge sta tus bit . (in master mode only) in master transmit mode : 0 = acknowledge was received from slave . 1 = acknowledge was not received from slave . bit 5 ackdt: acknowledge data bit. (in master mode only) in master receive mode : value that will be transmitte d when the user initiates an acknowledge sequence at the end of a receive. 0 = acknowledge . 1 = not acknowledge . b it 4 acken: acknowledge sequence enable bit . (in msp master mode only) in master receive mode : 0 = acknowledge sequence idle . 1 = initiate acknowledge sequence on sda and scl pins, and transmit ackdt data bit. automatically cleared by hardware. ? note : if the msp module is not in the idle mode, this bit may not be set (no spooling), and the mspbuf may not be written (or writes to the mspbuf a re disabled). b it 3 rcen: receive enable bit . (in master mode only) 0 = receive idle . 1 = enables receive mode for msp . ? note : if the msp module is not in the idle mode, this bit may not be set (no spooling), and the mspbuf may not be written (or writes to the mspbuf are disabled). b it 2 pen: stop condition enable bit . (in master mode only)
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 136 version 1.6 0 = stop condition idle . 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. ? note : if the msp module is not in the idle mode, this bit may not be set (no spooling), and the mspbuf may not be written (or writes to the mspbuf are disabled). b it 1 rsen: repeated start condition enabled bit . (in master mode only) 0 = repeated start condition idle. 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. ? note : if the msp module is not in the idle mode, this bit may not be set (no spooling), and the mspbuf may not be written (or writes to the mspbuf are disabled). b it 0 sen: start condition enable d bit . (in master mode only) 0 = start condition idle. 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. ? note : if the msp module is not in the idle mode, this bit may not be set (no spooling), and the mspbuf may not be w ritten (or writes to the mspbuf are disabled). 13.5 msp buffer register msp buf initial value = 0 00000 0 0 0edh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mspbuf mspbuf7 mspbuf6 mspbuf5 mspbuf4 mspbuf3 mspbuf2 mspbuf1 mspbuf0 read/write r/w r/w r/w r /w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit[7:0] mspbuf: msp buffer. 13.6 msp address register msp adr initial value = 0 00000 0 0 0eeh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mspadr mspadr7 mspadr6 mspadr5 mspadr4 mspadr3 mspadr2 mspadr1 ms padr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit[7:0] msp adr : msp a ddress .
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 137 version 1.6 13. 7 slave mode operation when an address is matched or data transfer after and address match is received, the hardware automatically will gene rate the acknowledge (ack_) signal, and load mspbuf (msp buffer register) with the received data from mspsr. there are some condition s that will cause msp function will not reply ack_ signal: ? data buffer already full: bf=1 (mspstat bit 0), when another tr ansfer was received . ? data overflow: mspov=1 (mspm1 bit 6), when another transfer was received . when bf=1, means mspbuf data is still not read by mcu, so mspsr will not load data into mspbuf, but mspirq and mspov bit will still set to 1. bf bit will be cle ar automatically when reading mspbuf register. mspov bit must be clear through by s of t ware. 13. 7 .1 addressing when msp slave function has been enabled, it will wait a start signal occur. following the start signal, 8 - bit address will shift into the msps r register. the data of mspsr[7:1] is compare with mspadr register on the falling edge of eight scl pulse, if the address are the same, the bf and mspov bit are both clear, the following event occur: 1. mspsr register is loaded into mspbuf on the falling edg e of eight scl pulse. 2. buffer full bit (bf) is set to 1, on the falling edge of eight scl pulse. 3. an ack_ signal is generated. 4. msp interrupt request mspirq is set on the falling edge of ninth scl pulse. status when data is received mspsp ? mspbuf reply an ac k_ signal set mspirq bf mspov 0 0 yes yes yes *0 *1 yes no yes 1 0 no no yes 1 1 no no yes data received action table note: bf=0, mspov=1 shows the software is not set properly to clear overflow register. 13. 7 .2 slave receiving when the r/w bi t of address byte =0 and address is matched, the r/w bit of mspstat is cleared. the address will be load into mspbuf. after reply an ack_ signal, msp will receive data every 8 clock. the ckp function enable or disable (default) is controlled by slrxckp bit and data latch edge - rising edge (default) or falling edge is controlled by c k e bit. when overflow occur, no acknowledge signal replied which either bf=1 or mspov=1. msp interrupt is generated in every data transfer. the mspirq bit must be clear by softwa re. following is the slave receiving diagram :
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 138 version 1.6 slrxckp=0 slrxckp=1 13. 7 .3 slave transmission after address match, the following r/w bit is set, mspstat bit 2 r/w will be set. the received address will be load to mspbuf and ack_ will be sent at nint h clock then scl will be hold low. transmission data will be load into mspbuf which also load to mspsr register. the master should monitor scl pin signal. the slave device may hold on the master by keep ckp low. when set. after load mspbuf, set ckp bit, ms pbuf data will shift out on the falling edge on scl signal. this will ensure the sda signal is valid on the scl high duty. an msp interrupt is generated on every byte transmission. the mspirq will be set on the ninth clock of scl. clear mspirq by software. mspstat register can monitor the status of data transmission. in slave transmission mode, an ack_ signal from master - receiver is latched on rising edge of ninth clock of scl. if ack_ = high, transmission is complete. slave device will reset logic and wait ing another start signal. if ack_= low, slave must load mspbuf which also mspsr, and set ckp=1 to start data transmission again. msp slave transmission timing diagram s r e c e i v i n g a d d r e s s a c k _ 1 a 7 2 a 6 3 a 5 4 a 4 5 a 3 6 a 2 7 a 1 8 9 a c k _ 1 d 7 2 d 6 3 d 5 4 d 4 5 d 3 6 d 2 7 d 1 9 8 d 0 1 d 7 2 d 6 3 d 5 4 d 4 5 d 3 6 d 2 7 d 1 8 d 0 9 p s d a s c l m s p i r q a c k _ b f m s p o v c k p r e c e i v i n g d a t a r e c e i v i n g d a t a c l e a r e d b y s o f t w a r e m s p o v = 1 , b e c a u s e m s p b u f s t i l l f u l l ( b f = 1 ) t e r m i n a t e b y m a s t e r a c k _ n o t s e n t c k p a l w a y s k e e p h i g h r e a d m s p b u f r / w = 0 s r e c e i v i n g a d d r e s s a c k _ 1 a 7 2 a 6 3 a 5 4 a 4 5 a 3 6 a 2 7 a 1 8 9 a c k _ 1 d 7 2 d 6 3 d 5 4 d 4 5 d 3 6 d 2 7 d 1 9 8 d 0 1 d 7 2 d 6 3 d 5 4 d 4 5 d 3 6 d 2 7 d 1 8 d 0 9 p s d a s c l m s p i r q a c k _ b f m s p o v c k p r e c e i v i n g d a t a r e c e i v i n g d a t a c l e a r e d b y s o f t w a r e m s p o v = 1 , b e c a u s e m s p b u f s t i l l f u l l ( b f = 1 ) t e r m i n a t e b y m a s t e r a c k _ n o t s e n t r e a d m s p b u f r / w = 0 s e t c k p a f t e r r e a d m s p b u f s e t c k p , n o t r e a d m s p b u f s e t c k p s r e c e i v i n g a d d r e s s a c k _ 1 a 7 2 a 6 3 a 5 4 a 4 5 a 3 6 a 2 7 a 1 8 9 r / w = 0 a c k _ 1 2 d 6 3 d 5 4 d 4 5 d 3 6 d 2 7 d 1 8 d 0 9 p s d a s c l m s p i r q b f c k p t r a n s m i s s i o n d a t a c l e a r e d b y s o f t w a r e m s p b u f i s w r i t i n g b y s o f t w a r e r / w = 1 s e t c k p a f t e r w r i t i n g t o m s p b u f } i n t e r r u p t s e r v i c e r o u t i n e d 7
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 139 version 1.6 13. 7 .4 general call address in msp bus, the first 7 - byte is the slave address. only the address match mspadr the slave will response an ack_. the exception is the general call address which can address all slave devices. when this address occur, all devices should response an acknowledge. the general call addres s is a special address which is reserved as all D0 of 7 - b it s address. the general call address function is control by gcen bit. set this bit will enable general call address and clear it will disable. when gc e n=1, following a start signal, 8 - bit will shif t into mspsr and the address is compared with mspad r and also the general call address which fixed by hardware. if the genera l call address matches, the mspsr data is transferred into mspbuf, the bf flag bit is set, and in the falling edge of the ninth clo ck (ack_) mspirq flag set for interrupt request. in the interrupt service routine, reading mspbuf can check if the address is the general call address or device specific. general call address timing diagram 13. 7 .5 slave wake up when mcu enter power d own mode, if ms p enb bit is still set, mcu can wake - up by matched device address. the address of msp bus following start bit, 8 - bits address will shift into mspsr, if address matched, an not acknowledge will response on the ninth clock of scl and mcu will b e wake - up, mspwk set and start wake - up procedure but mspirq will not set and mspsr data will not load to mspubf. after mcu finish wake - up procedure, msp will be in idle status and waiting masters start signal. control register bf, mspirq, mspov and mspbuf will be the same status/data before power down. if address not matches, a not acknowledge is still sent on the ninth clock of scl, but mcu will be not wake - up and still keep in power down mode. msp wake - up timing diagram: add ress not matched s a c k _ 1 2 3 4 5 6 7 8 9 0 1 d 7 2 d 6 3 d 5 4 d 4 5 d 3 6 d 2 7 d 1 9 8 d 0 s d a s c l m s p i r q b f m s p o v g c e n r e c e i v i n g d a t a c l e a r e d b y s o f t w a r e r e a d m s p b u f r / w = 0 g e n e r a l c a l l a d d r e s s 1 a c k _ a f t e r a c k _ , s e t i n t e r r u p t a d d r e s s c o m p a r e t o g e n e r a l c a l l a d d r e s s s r e c e i v i n g a d d r e s s 1 a 7 2 a 6 3 a 5 4 a 4 5 a 3 6 a 2 7 a 1 8 9 a c k _ p s d a s c l m s p i r q b f r / w 0 0 w a k e - u p 0 m s p w k 0 m c u m o d e c l e a r m s p w k , s e t f c p u m 0 ( p o w e r d o w n ) n o r m a l m o d e p o w e r d o w n m o d e
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 140 version 1.6 msp wake - up timing diagram: address matched ? note: 1. msp function only can work on normal mode, when wake - up from power down mode, mcu must operate in normal mode before master sent start signal. ? note:2. in msp wake - up, if the address not match, mcu will keep in power down mode. ? note 3. clear mspwk before enter power down mode by software for wake - up indication. s r e c e i v i n g a d d r e s s 1 a 7 2 a 6 3 a 5 4 a 4 5 a 3 6 a 2 7 a 1 8 9 a c k _ p s d a s c l m s p i r q b f r / w w a k e - u p n o r m a l m o d e c l e a r m s p w k , s e t f c p u m 0 ( p o w e r d o w n ) m c u w a k e - u p s t a r t w a r m - u p m c u m o d e w a r m - u p t i m e n o r m a l m o d e ( o p - c o d e e x e c u t i n g ) p o w e r d o w n m o d e s r e c e i v i n g a d d r e s s a c k _ 1 a 7 2 a 6 3 a 5 4 a 4 5 a 3 6 a 2 7 a 1 8 9 a c k _ 1 d 7 2 d 6 3 d 5 4 d 4 5 d 3 6 d 2 7 d 1 9 8 d 0 r e c e i v i n g d a t a c l e a r e d b y s o f t w a r e r e a d m s p b u f r / w = 0 m s p w k c l e a r m s p w k b y s o f t w a r e
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 141 version 1.6 13. 8 master mode operation master mode of msp operation from a start signal and end by stop si gnal. the start (s) and stop (p) bit are clear when reset or msp function disabled. in master mode the scl and sda line are controlled by msp hardware. following events will set msp interrupt request (mspirq), if mspien set, interrupt occurs. ? start condit ion. ? stop condition. ? data byte transmitted or received. ? acknowledge transmit. ? repeat start. 13. 8 .1 master mode support master mode enable when mspc and mspenb bit set. once the master mode enabled, the user had following six options. ? send a start signal on scl and sda line. ? send a repeat start signal on scl and sda line. ? write to mspbuf register for data or address byte transmission. ? send a stop signal on scl and sda line. ? configuration msp port for receive data. ? send an acknowledge at the end of a recei ved byte of data. 13. 8 .2 msp rate generator (mrg) in msp mode, the msp rate generators reload value is located in the lower 7 bit of mspadr register. when mrg is loaded with the register, the mrg count down to 0 and stop until another reload has taken p lace. in msp mater mode mrg reload from mspadr automatically. if clock arbitration occur for instance (scl pin keep low by slave device), the mrg will reload when scl pin is detected high. scl clock rate = fcpu/(mspadr)*2 for example, if we want to set 4 00khz in 4mhz fcpu, the mspadr have to set 0x05h. mspadr=4mhz/400khz*2=5 msp rate generator block diagram m s p c ( m s p m 1 b i t 0 ) m s p a d r m r g d o w n c o u n t e r m s p c s c l r e l o a d c o n t r o l f c p u / 4 s c l c l o c k o u t
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 142 version 1.6 mrg timing diagram with and without clock arbitration (mspadr=0x03) 13. 8 .3 msp master mode start condition to gene rate a start signal, user sets sen bit (mspm2.0). when sda and scl pin are both sampled high, msp rate generator reload mspadr[6:0], and starts down counter. when sda and scl are both sampled high and mrg overflow, sda pin is drive low. when scl sampled hi gh, and sda transmitted from high to low is the start signal and will set s bit (mspstat.3). mrg reload again and start down counter. sen bit will be clear automatically when mrg overflow, the mrg is suspend leaving sda line held low, and start condition i s complete. wcol status flag if user write to mspbuf when start condition processing, then wcol is set and the content of mspbuf data is un - changed. (the writer doesnt occur) start condition timing diagram 13. 8 .4 msp maste r mode repeat start condition when msp logic module is idle and rsen set to 1, repeat start progress occurs. rsen set and scl pin is sampled low, mspadr[6:0] data reload to msp rate generator and start down counter. the sda pin is release to high in one m sp rate generate counter (t b mrg b ). when the mrg is overflow, if sda is sampled high. scl will be brought high. when scl is sampled high, mspadr reload to mrg and start down counter. sda and scl must keep high in one t b mrg b period. in the next t b mrg b period , sda will be brought low when scl is sampled high, then rsen will clear automatically by hardware and mrg will not reload, leaving sda pin held low. once detect sda and scl occur start condition, the s bit will be set (mspstat.3). mspirq will not set unti l mrg overflow. ? note: 1. while any other event is progress, set rsen will take no effect. ? note:2. a bus collision during the repeat start condition occur: sda is sampled low when scl goes from low to high . wcol status flag if user write to mspbuf when r epeat start condition processing, then wcol is set and the content of mspbuf data is un - changed. (the writer doesnt occur) s d a s c l 3 2 1 0 3 2 1 0 3 2 1 0 3 2 n o c l o c k a r b i t r a t i o n d x - 1 d x - 2 m r g d o w n c o u n t e r m r g r e l o a d d x s d a s h i f t i n n e x t b i t d a t a c l o c k a r b i t r a t i o n s l a v e r e l e a s e s c l c l o c k , s c l a l l o w e d t o t r a n s i t i o n h i g h . f c p u / 4 s c l i s s a m p l e d h i g h , r e l o a d o c c u r r e d a n d m r g d o w n c o u n t e r s t a r t s c o u n t s d a s c l 1 s t - b i t 2 n d - b i t c o m p l e t e s r a r t s i g n a l , h a r d w a r e c l e a r s e n b i t , s e t m s p i r q b i t s d a = 1 s c l = 1 t m r g t m r g s e t s b i t ( m s p s t a t . 3 ) s w r i t e m s p b u f h e r e w r i t e s e n h e r e t m r g t m r g t m r g
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 143 version 1.6 repeat start condition timing diagram 13. 8 .5 acknowledge sequence timing an acknowledge sequence is enabled when set acken (m spm2.4). scl is pulled low when set acken and the content of the acknowledge data bit is present on sda pin. if user wished to reply a n acknowledge, ackdt bit should be cleared. if not, set ackdt bit before starting a acknowledge sequence. scl pin will be release (brought high) when msp rate generator overflow. msp rate generator start a t b mrg b period down counter, when scl is sampled high. after this period, scl is pulled low, and acken bit is clear automatically by hardware. when next mrg overflow again, msp goes into idle mode. wcol status flag if user write to mspbuf when acknowledge sequence processing, then wcol bit is set and the content of mspbuf data is un - changed. (the writer doesnt occur) acknowledge sequence timing diagram 13. 8 .6 msp maste r mode stop condition timing at the end of received/transmitted, a stop signal present on sda pin by setting the stop bit register, pen (mspm2. 2 ). at the end of receive/transmit, scl goes low on the failing edge of ninth clock. master will set sda go low, when set pen bit. when sda is sampled low, msp rate generator is reloaded and start count down to 0. when mrg overflow, scl pin is pull high. after one t b mrg b period, sda goes high. when sda is sampled high while scl is high, bit p is set. pen bit is clea r after next one t b mrg b period, and mspirq is set. wcol status flag if user write to mspbuf when a stop condition is processing, then wcol bit is set and the content of mspbuf data is un - changed. (the writer doesnt occur) s d a s c l 1 s t - b i t s d a = 1 s c l n o c h a n g e r s = r e p e a t s t a r t w r i t e r s e n h e r e t m r g t m r g r i s i n g e d g e o f n i n t h c l o c k , e n d o f t r a n s m i s s i o n s d a = 1 , s c l = 1 t m r g s e t s b i t c o m p l e t e o f s t a r t b i t , h a r d w a r e c l e a r r s e n b i t a n d s e t m s p i r q t m r g t m r g w r i t e t o m s p b u f h e r e s d a s c l d 0 s e t m s p i r q a t t h e e n d o f r e c e i v e t m r g t m r g 8 9 w r i t e a c k e n = 1 , a c k d t = 0 a c k n o w l e d g e s e q u e n c e s t a r t h e r e a c k _ a c k e n c l e a r e d a u t o m a t i c a l l y m s p i r q c l e a r m s p i r q b y s o f t w a r e s e t m s p i r q a t t h e e n d o f a c k n o w l e d g e s e q u e n c e c l e a r m s p i r q b y s o f t w a r e
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 144 version 1.6 st op condition sequence timing diagram 13.8 . 7 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeat start, stop condition that scl pin allowed to float high. when scl pin is allowed float high, the msp rate gen erator (mrg) suspended from counting until the scl pin is actually sampled high. when scl is sampled high, the mrg is reloaded with the content of mspadr[6:0], and start down counter. this ensure that scl high time will always be at least one mrg overflow time in the event that the clock is held low by an external device. clock arbitration sequence timing diagram s d a s c l t m r g t m r g f a l l i n g e d g e o f n i n t h e d g e p p b i t i s s e t t m r g s e t p e n h e r e s d a g o e s l o w b e f o r e t h e r i s i n g e d g e o f s c l t o s e t u p s t o p s i g n a l s c l g o e s h i g h o n n e x t t m r g t m r g p e n i s c l e a r b y h a r d w a r e a n d m s p i r q b i t i s s e t s d a s c l t m r g m r g o v e r f l o w , r e l e a s s c l , i f s c l = 1 , r e l o a d m r g w i t h m s p a d r a n d s t a r t c o u n t d o w n t o m e a s u r e h i g h t i m e i n t e r v a l s c l p i n s a m p l e d o n c e e v e r y f c p u / 4 , h o l d o f m r g u n t i l s c l i s s a m p l e d h i g h t m r g t m r g m r g o v e r f l o w , r e l e a s e s c l , s l a v e d e v i c e h e l d t h e s c l l o w s c l = 1 , m r g s t a r t c o u n t i n g c l o c k h i g h i n t e r v a l
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 145 version 1.6 13.8 . 8 master mode transmission transmission a data byte, 7 - bit address or the eight bit data is accomplished by simply write to mspbuf reg ister. this operation will set the buffer full flag bf and allow msp rate generator start counting. after write to mspbuf, each bit of address will be shifted out on the falling edge of scl until 7 - bit address and r/w bit are complete. on the fa l ling edge of eighth clock, the master will pull low sda fort slave device respond with an acknowledge. on the ninth clock falling edge, sda is sampled to indicate the address already accept by slave device. the status of the ack bit is load into ackstat status bit. then mspirq bit is set, the bf bit is clear and the mrg is hold off until another write to the mspbuf occurs, holding scl low and allow sda floating. bf status flag in transmission mode, the bf bit is set when user writes to mspbuf and is cleared automat ically when all 8 bit data are shift out. wcol flag if user write to mspbuf during transmission sequence in progress, the wcol bit is set and the content of mspbuf data will unchanged. ackstat status flag in transmission mode, the ackstat bit is cleared when the slave has sent an acknowledge (ack_=0), and is set when slave does not acknowledge (ack_=1). a slave send an acknowledge when it has recognized its address (including general call), or when the slave has properly received the data. msp master t ransmission mode timing diagram s t r a n s m i t a d d r e s s a c k _ = 0 1 a 7 2 a 6 3 a 5 4 a 4 5 a 3 6 a 2 7 a 1 8 9 a c k _ 1 2 d 6 3 d 5 4 d 4 5 d 3 6 d 2 7 d 1 8 d 0 9 p s d a s c l m s p i r q b f s e n t r a n s m i s s i o n d a t a c l e a r e d b y s o f t w a r e r / w = 0 w r i t e s e n = 1 , s t a r t c o n d i t i o n b e g i n s s e n = 0 d 7 p e n r e d _ w r t w r i t e a d d r e s s a n d r / w t o m s p b u f s t a r t t r a n s m i t w r i t e m s p b u f s e n c l e a r e d b y h a r d w a r e , a f t e r s t a r t c o n d i t i o n f r o m s l a v e , c l e a r a c k s t a t s c l h e l d l o w , w h i l e m a s t e r r e s p o n s e m s p i r q c l e a r e d b y s o f t w a r e a c k s t a t = 1 c l e a r e d b y s o f t w a r e s e r v i c e r o u t i n e o f m s p i n t e r r u p t w r i t e m s p b u f
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 14 6 version 1.6 13.8 . 9 master mode receiving master receiving mode is enable by set rcen bit. the mrg start counting and when scl change state from low to high, the data is shifted into mspsr. after the falling edge of eighth clock, th e receive enable bit (rcen) is clear automatically, the contents of msp are load into mspbuf, the bf flag is set, the mspirq flag is set and mrg counter is suspended fro m counting, holding scl low. the msp is now in idle mode and awaiting the next operatio n command. when the mspbuf data is read by software, the bf flag is clea r automatically. by setting acken bit, user can send an acknowledge bit at the end of receiving. bf status flag in rece ption mode, the bf bit is set when an address or data byte is lo aded into mspbuf from mspsr. it is cleared automatically when mspbuf is read. mspov flag in receive operation, the mspov bit is set when another 8 - bit are received into mspsr, and the bf bit is already set from previous reception . wcol flag if user write to mspbuf when a receive is already progress, the wcol bit is set and the content of mspbuf data will unchanged. msp master receiving mode timing diagram s t r a n s m i t a d d r e s s t o s l a v e a c k _ = 0 1 a 7 2 a 6 3 a 5 4 a 4 5 a 3 6 a 2 7 a 1 8 9 a c k _ 1 2 d 6 3 d 5 4 d 4 5 d 3 6 d 2 7 d 1 8 s d a s c l m s p i r q b f m s p o v r e c e i v i n g d a t a f r o m s l a v e c l e a r e d b y s o f t w a r e r / w = 1 w r i t e s e n = 1 , s t a r t c o n d i t i o n b e g i n s s e n = 0 d 7 a c k e n w r i t e a d d r e s s a n d r / w t o m s p b u f s t a r t t r a n s m i t w r i t e m s p b u f f r o m s l a v e , c l e a r a c k s t a t c l e a r e d b y s o f t w a r e 1 2 d 6 3 d 5 4 d 4 5 d 3 6 d 2 7 d 1 p 9 a c k _ 9 8 d 0 c l e a r e d b y s o f t w a r e w r i t e r c e n = 1 d 0 r c e n c l e a r e d a u t o m a t i c a l l y w r i t e a c k e n = 1 s t a r t a c k n o w l e d g e s e q u e n c e , s d a = a c k d t = 0 a c k f r o m m a s t e r s d a = a c k d t = 0 w r i t e r c e n = 1 , s t a r t n e x t r e c e i v e r e c e i v i n g d a t a f r o m s l a v e r c e n c l e a r e d a u t o m a t i c a l l y w r i t e a c k e n = 1 s t a r t a c k n o w l e d g e s e q u e n c e , s d a = a c k d t = 1 a c k _ i s n o t s e n t w r i t e p e n = 1 h e r e m a s t e r t e r m i n a l t r a n s f e r s e t m s p i r q a t t h e e n d o f r e c e i v e s e t m s p i r q a t t h e e n d o f a c k n o w l e d g e s e q u e n c e d a t a s h i f t e d i n f a i l i n g e d g e o f s c l s e t m s p i r q a t t h e e n d o f r e c e i v e s e t m s p i r q a t t h e e n d o f a c k n o w l e d g e s e q u e n c e p b i t a n d m s p i r q b i t i s s e t l a s t b i t i s s h i f t e d i n t o m s p s r , m s p b u f i s n o t r e a d . m s p b u f i s s t i l l f u l l , m s p o v s e t d 7
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 147 version 1.6 14 flash 1 4 .1 overview the sn8f22 8 0 series usb mcu integrated device feature in - syst em programmable (isp) flash memory for convenient, upgradeable code storage. the flash memory may be programmed via the sonix 8 bit mcu programming interface or by application code and usb interface for maximum flexibility. the sn8f22 8 0 provides security o ptions at the disposal of the designer to prevent unauthorized access to information stored in flash memory. ? the mcu is stalled during flash write (program) and erase operations, although peripherals (usb, timers, wdt, i/o, pwm, etc.) remain active. ? inte rrupts will disable by firmware during a flash write or erase operation. ? the flash page containing the code option (rom address 0x2 f8 0 ~ 0x2 f ff) cannot be erased from application code when the code options security enable. ? watch dog timer should be clea r before the flash write or erase operation. ? the erase operation sets all the bits in the flash page to logic 1. ? hardware will hold system clock and automatically move out data from ram and do programming, after programming finished, hardware will releas e system clock and let mcu execute the next instruction.( r ecommend add two nop instructions after this active) .
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 148 version 1.6 1 4 .2 flash programming/erase control register 0bah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pecmd pecmd7 pecmd6 pecmd5 pecmd4 pecmd3 pecmd2 pecmd1 pecmd0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 bit [7:0] pecmd[7:0]: 0x5a: page p rogram (32 words /page ) , 0xc3: page e rase (128 words /page ) 1 4 . 3 programming/erase address register 0bbh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pe rom l pe rom l7 peroml6 peroml5 peroml4 peroml3 peroml2 peroml1 peroml0 read/write r/ w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit [7:0] peroml [7:0]: define the target starting low byte address [7:0] of flash m emory (1 2 k x 16) which is going to be programmed or erased. 0bch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 peromh peromh7 peromh6 peromh5 peromh4 peromh3 peromh2 peromh1 peromh0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit [7:0] peromh [7:0]: define the target starting high address [15:8] of flash memory (1 2 k x 16) which is going to be programmed or erased. the valid page erase starting ad dresses are 0x0, 0x80, 0x100, 0x180, 0x 200, 0x280, 0x 300, 0x380 0x2 f 80. th e page erase function is used to erase a page of 128 contiguous words in flash rom. the valid page program starting addresses are 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0, 0xc0, 0xe0 0x2 f e0. the page program function is used to program a page of 32 contiguous words in flash rom.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 149 version 1.6 1 2 kx16 flash 0000h reset vector user reset vector jump to user start address 0001h general purpose area . . 0007h 0008h interrupt vector user interrupt vector 0009h general purpose area user program . . 000fh 0010h 0011h . . . . . 2f80h security protect & reserved (code option) . end of user program 2 f fch 2 f fdh 2 f feh 2 f ffh flash rom mapping note: 1. if the code option security = 1, the flash rom address = 0x2 f8 0 ~ 0x2 f ff will not allow to do the page erase and page program.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 150 version 1.6 1 4 . 4 programming/erase data register 0bdh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 peraml peraml7 peraml6 peraml5 peraml4 peraml3 peraml2 peraml1 peraml0 re ad/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0b e h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 peramcnt peramcnt4 peramcnt3 peramcnt2 peramcnt1 peramcnt0 - peraml 9 peraml8 read/write r/w r/w r/w r/w r/w - - r/w after reset 0 0 0 0 0 - - 0 { peramcnt [ 1: 0], peraml [ 7:0] } : define the starting ram address [9 :0] , which stores the data wanted to be programmed. the valid ram addresses are 00h ~ 07fh and 0100h ~ 0 27 fh. peramcnt [7:3] : defines the number of words wanted to be prog rammed. the maximum peramcnt [ 7:3] is 01fh, which program 32 words (64 bytes ram) to the flash. the minimum peramcnt [ 7:3] is 00h, which program only 1 word to the flash. 14.4.1 flash in - system - programming mapping address ram (byte) flash rom (word) bit7 ~ bit0 bit15 ~ bit8 bit7 ~ bit0 x data0 y data1 data0 x+1 data1 y+1 data3 data2 x+2 data2 => y+2 x+3 data3 y+3 x+n datan y+m datan datan - 1
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 151 version 1.6 15 instruction table field mnemonic description c dc z cycle mov a,m a ? m - - ? 1 m mov m,a m ? a - - - 1 o b0mov a,m a ? m (bank 0) - - ? 1 v b0mov m,a m (bank 0) ? a - - - 1 e mov a,i a ? i - - - 1 b0mov m,i m ? i, Dm only supports 0x80~0x87 registers (e.g. pflag,r,y,z) - - - 1 xch a,m a ? ? m - - - 1+n b0xch a,m a ? ? m (bank 0) - - - 1+n movc r, a ? rom [y,z] - - - 2 adc a,m a ? a + m + c, if occur carry, then c=1, else c=0 ? ? ? 1 a adc m,a m ? a + m + c, if occur carry, then c=1, else c=0 ? ? ? 1+n r add a,m a ? a + m, if occur carry, then c=1, else c=0 ? ? ? 1 i add m,a m ? a + m, if occur carry, then c=1, else c=0 ? ? ? 1 +n t b0add m,a m (bank 0) ? m (bank 0) + a, if occur carry, then c=1, else c=0 ? ? ? 1+n h add a,i a ? a + i, if occur carry, then c=1, else c=0 ? ? ? 1 m sbc a,m a ? a - m - /c, if occur borrow, then c=0, else c=1 ? ? ? 1 e sbc m,a m ? a - m - /c , if occur borrow, then c=0, else c=1 ? ? ? 1+n t sub a,m a ? a - m, if occur borrow, then c=0, else c=1 ? ? ? 1 i sub m,a m ? a - m, if occur borrow, then c=0, else c=1 ? ? ? 1+n c sub a,i a ? a - i, if occur borrow, then c=0, else c=1 ? ? ? 1 a nd a,m a ? a and m - - ? 1 l and m,a m ? a and m - - ? 1+n o and a,i a ? a and i - - ? 1 g or a,m a ? a or m - - ? 1 i or m,a m ? a or m - - ? 1+n c or a,i a ? a or i - - ? 1 xor a,m a ? a xor m - - ? 1 xor m,a m ? a xor m - - ? 1+n xor a,i a ? a xor i - - ? 1 swap m a (b3~b0, b7~b4) ? m(b7~b4, b3~b0) - - - 1 p swapm m m(b3~b0, b7~b4) ? m(b7~b4, b3~b0) - - - 1+n r rrc m a ? rrc m ? - - 1 o rrcm m m ? rrc m ? - - 1+n c rlc m a ? rlc m ? - - 1 e rlcm m m ? rlc m ? - - 1+n s cl r m m ? 0 - - - 1 s bclr m.b m.b ? 0 - - - 1+n bset m.b m.b ? 1 - - - 1+n b0bclr m.b m(bank 0).b ? 0 - - - 1+n b0bset m.b m(bank 0).b ? 1 - - - 1+n cmprs a,i zf,c ? a - i, if a = i, then skip next instruction ? - ? 1 + s b cmprs a,m zf,c ? a C m, if a = m, then skip next instruction ? - ? 1 + s r incs m a ? m + 1, if a = 0, then skip next instruction - - - 1+ s a incms m m ? m + 1, if m = 0, then skip next instruction - - - 1+n+s n decs m a ? m - 1, if a = 0, then skip next instructi on - - - 1+ s c decms m m ? m - 1, if m = 0, then skip next instruction - - - 1+n+s h bts0 m.b if m.b = 0, then skip next instruction - - - 1 + s bts1 m.b if m.b = 1, then skip next instruction - - - 1 + s b0bts0 m.b if m(bank 0).b = 0, then skip next instruction - - - 1 + s b0bts1 m.b if m(bank 0).b = 1, then skip next instruction - - - 1 + s jmp d pc15/14 ? rompages1/0, pc13~pc0 ? d - - - 2 call d stack ? pc15~pc0, pc15/14 ? rompages1/0, pc13~pc0 ? d - - - 2 m ret pc ? stack - - - 2 i reti pc ? stack, and to enable global interrupt - - - 2 s push to push acc and pflag (except nt0, npd bit) into buffers. - - - 1 c pop to pop acc and pflag (except nt0, npd bit) from buffers. ? ? ? 1 nop no operation - - - 1 note: 1. m is system register or ram. if m is system registers then n = 0, otherwise n = 1. 2. if branch condition is true then s = 1, otherwise s = 0.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 152 version 1.6 16 development tool sonix provides ice (in circuit emulation), ide ( integrat ed development environment) , ev - kit and firmware library for usb application development. ice and ev - kit are external hardware device and ide is a friendly user interface for firm ware development and emulation. 1 6 .1 ice (in circuit emulation) the ice called Dsn8ice2k plus .
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 153 version 1.6 the ice called Dsn8ice2k plus ii . ? note 1 : sn8ice2k plus shall be used with sn8f2280 ev - kit v2 for fw development and emulation . ? note 2 : sn8ice2k plus ii shall be used with sn8f2280 ev - kit v3 for fw development and emulation .
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 154 version 1.6 1 6 .2 sn8f 2280 ev - k it sn8f 2280 ev - kit includes ice interface, gpio interface, usb interface, uart interface, sio interface, msp interface, pwm interface, and vreg 3.3v power supply. ? ice interface: interface connected to sn8ice2k plus . ? gpio interface: sn8f22 88 p ackage form connector. ? usb interface: usb mini - b connector. ? uart interface: interface connected to universal asynchronous receiver/transmitter (uart) connector. ? sio interface: interface connected to serial input/output transceiver (sio) connector. ? msp inte rface: interface connected to main series port (msp) connector. ? pwm interface: output the pwm signal to pwm connector. ? vreg 3.3v power supply: use sn8p221 2 s vreg to supply 3.3v power for vreg 33 pin. the outline of sn8f 2280 ev - kit v2 is as following.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 155 version 1.6 the outline of sn8f2280 ev - kit v3 is as following. ? con1: ice interface connected to sn8ice2k plus. ? j 1 : jumper to connect between the 5v vdd from sn8ice2k plus and vdd on sn8f22 88 package fr o m socket. ? j 7 : usb mini - b connector. ? u 11 : sn8p2212 to s upply 3.3v power for vreg 33 pin and usb phy . ? jp2 : sn8f22 88 con nector for users target board. ? jp3: sn8f2288 to supply p0 and p1 i/o level change interrupt function. ? j2 - j4: uart i nterface connected to rs - 232 connector . ? j p4 : sio interface connector, msp inte rface connector, uart interface connector , and pwm interface connector. ? note 1 : in the ev - kit, uart and msp are not built - in open - drain function, such as p0.5/urx, p0.6/utx , p1.0 /scl, p1.1/sda. these are different from ic . ? note 2 : in the ev - kit, p ort 2 , p0.5/urx, p0.6/utx, p1.0/scl, p1.1/sda, and p5.5/pwm2 are built - in 1k ohm external pu ll up resister s . ? note 3 : in the ev - kit, port 2 is not schmitt trigger structure . th is is different from ic . ? note 4 : sn8ice2k plus shall be used with sn8f2280 ev - kit v2 f or fw development and emulation . ? note 5 : sn8ice2k plus ii shall be used with sn8f2280 ev - kit v3 for fw development and emulation .
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 156 version 1.6 1 6 .3 sn8f 2280 transition board sn8f 2280 transition boards is designated to ic lqfp package. the following show s the transition board outline for sn8f22 88 . among the board, both c1 and c2 must be welded by 1uf capacitor.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 157 version 1.6 17 electrical characteristic 1 7 .1 absolute maximum rating supply voltage (vdd). - 0.3v ~ 5.5 v input in voltage (vin). vss C 0.2v ~ vdd + 0.2v opera ting ambient temperature (topr) sn8f22 88f ... .. ... . 0 ? c ~ + 70 ? c storage ambient temperature (tstor) . C 30 ? c ~ + 125 ? c 1 7 .2 electrical characteristic (all of voltages refer to vss, vdd = 5.0v, fosc = 12 mhz, ambient temperature is 25 ? c unless otherwise note.) parameter sym. description min. typ. max. unit operating voltage vd d1 normal mode except usb transmitter 4 .0 5 5.5 v vdd2 usb mode 4.25 5 5.25 v ram data retention voltage vdr - 1.5* - v vdd rise rate vpor vdd rise rate to ensure power - on reset 0.05 - - v/ms input low voltage vil1 p0, p1, p4, p5 input ports vss - 0 . 2 vdd v vil2 p2 input ports vss - 0.2 vreg33 v input high voltage vih1 p0, p1, p4, p5 input ports 0. 8 vdd - vdd v vih2 p2 input ports 0.8 vreg33 - v reg33 v input voltage vin1 p0, p1, p4 , p5 i/o ports input voltage range - 0.5 - vdd+0.5 v vin2 p2 i/o ports input voltage range - 0.3 - vreg33 +0.3 v output voltage voh1 p0, p1, p4 , p5 output ports 0 - vdd v voh2 p2 output ports 0 - vreg33 v reset pin leakage current ilekg vin = vdd - - 2 ua i/o port pull - up resistor rup1 rup1 p0, p1, p4, p5 ?s vin = vss, vdd = 5v 25 40 * 70 k ? i/o port pull - up resistor rup2 rup2 p2s vin = vss, vdd = 5v 3 0 55 * 1 0 0 k ? d+ pull - up resistor rd+ vdd = 5 v, vreg = 3.3v 1 1.5 1.65 k ? i/o port input leakage current ilekg pull - up resistor disable, vin = vdd - - 2 ua i/o outp ut source current ioh 1 p0, p1, p4 , p5 i/o ports output source current, vop 1 = vdd C 1v 15 20* ma ioh2 p 2 i/o ports output source current, vop 2 = v reg33 C 1v 1 2* sink current iol 1 p0, p1, p4 , p5 i/o ports sink current, vop 1 = vss + 0.4v 15* 20 iol2 p 2 i/o ports sink current, vop 2 = vss + 0.4v 2* 3 intn trigger pulse width tint0 int0 interrupt request pulse width 2/fcpu - - cycle page erase (128 words) terase flash rom page erase time - 25* 50 ms page program (32 words) tpg flash rom page program time (program 32 words) - 1* 2 ms vreg33 regulator current ivreg 33 vreg33 max regulator output current, vcc > 4.35 volt with 10uf to gnd - - 60 ma vreg33 regulator gnd current ivreg33 _gnl no loading. vreg33 pin output 3.3v ((regulator enable) - 70 100 ua vreg25 regulator gnd current ivreg25 _gnl no loading.vreg25 pin output 2.5v ((regulator enable) - 120 150 ua vreg33 regulator output voltage vreg1 vcc > 4.35v, 0 < temp < 40c, ivreg Q 60 ma with 10uf to gnd 3.0 - 3.6 v vreg2 vcc > 4.35v, 0 < temp < 40c, ivreg Q 25 ma with 10uf to gnd 3.1 - 3.6 v
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 158 version 1.6 supply current idd1 normal mode (no loading, fcpu = fosc/ 1 ) vdd= 5v, 12mhz - 10 15 ma idd2 slow mode (internal low rc) vdd= 5v, 1 2khz - 190 250 ua idd3 sleep mode vdd= 5v - 190 250 ua idd4 g reen mode (no loading, fcpu = fosc/4 watchdog disable) vdd= 5v, 12mhz - 5 10 ma vdd=5v, ilrc 1 2khz - 190 250 ua lvd voltage vdet 1 low voltage reset level middle. 1.8 2.4 2.9 v vdet 2 low voltage reset level high . 2.8 3.6 4.2 5 v * these parameters a re for design reference, not tested.
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 159 version 1.6 18 f lash rom programming pin programming information of sn8f 22 8 0 series chip name sn8f 22 88f /j SN8F2283j ez writer / mp writer connector flash ic / jp3 pin assigment numbe r name number pin number pin number pin nu mber pin number pin 1 vdd 7 29 vdd 11 23 vdd 2 gnd 16 25 vss 2 12 13 19 vss 3 clk 47 p 1 . 4 5 p1.4 4 ce 5 pgm 1 p1. 2 7 p1.2 6 oe 46 p 1 . 5 4 p1.5 7 d1 8 d0 9 d3 10 d2 11 d5 12 d4 13 d7 14 d6 15 vdd 16 - 17 hls 18 rst 19 - 20 alsb/pdb 48 p1. 3 6 p1.3
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 160 version 1.6 19 package information 1 9 .1 lqfp 48 pin symbols min nor max (mm) a - - 1.6 a1 0.05 - 0.15 a2 1.35 - 1.45 c1 0.09 - 0.16 d 9.00 bsc d1 7.00 bsc e 9.00 bsc e1 7.00 bsc e 0.5 bsc b 0.17 - 0.27 l 0.45 - 0.75 l1 1 ref
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 161 version 1.6 19.2 qf n 48 pin sy mbol dimension (mm) dimension (mil) min. nom. max. min. nom. max. a 0.80 0.85 0.90 31.5 33.5 35.4 a1 0 0.02 0.05 0 0.79 1.97 a3 0.203 ref 8 ref b 0.18 0.25 0.30 7.1 9.8 11.8 d 7.00 bsc 276 bsc d2 5.10 5.35 5.60 201 210 221 e 7.00 bsc 276 bsc e2 5 .10 5.35 5.60 201 210 221 e 0.50 bsc 19.7 bsc k 0.2 7.9 l 0.30 0.40 0.50 11.8 15.7 19.7 y 0.08 3.15
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 162 version 1.6 19.3 qf n 2 4 pin
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 163 version 1.6 20 marking definition 20 .1 introduction there are many different types in sonix 8 - bit mcu productio n line. this note listed the production definition of all 8 - bit mcu for order or obtain information. 20 .2 marking indetification system title sonix 8-bit mcu production rom type p=otp f=flash memory material b = pb-free package g = green package temperature range - = 0 ~ 70 ~ 85 shipping package w = wafer h = dice k = sk-dip p = p-dip s = sop x = ssop f = lqfp j = qfn device device part no. sn8 x part no. x x x
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 164 version 1.6 20 .3 marking example name rom type device package temperature material sn8f22 88 fg flash memory 22 88 lqfp 0 ~70 green package sn8f 22 88 w flash memory 22 88 wafer 0 ~70 - sn8f 22 88 h flash memory 22 88 dice 0 ~70 - SN8F2283jg flash memory 22 88 qfn 0 ~70 green package 20 .4 datecode system x x x x xxxxx year month 1=january 2=february . . . . 9=september a=october b=november c=december sonix internal use day 1=01 2=02 . . . . 9=09 a=10 b=11 . . . . 03= 2003 04= 2004 05= 2005 06= 2006 . . . .
sn8f2280 series usb 2.0 full - speed 8 - b it m icro - c ontroller sonix technology co., ltd page 165 version 1.6 sonix reserves the right to make change without further notice to any products herein to improve reliability, function or design. sonix does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. sonix products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the sonix product could create a situation where personal injury or death may occur. should buyer purchase or use sonix products for any such unintended or unauthorized application. buyer shall indemnify and hold sonix and its officers , employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal inju ry or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part. main office: address: 10f - 1, no. 36, taiyuan stree., chupei city, hsinchu, taiwan r.o.c. tel: 886 - 3 - 5600 888 fax: 886 - 3 - 5600 889 taipei office: address: 15f - 2, no. 171, song ted road, taipei, taiwan r.o.c. tel: 886 - 2 - 2759 1980 fax: 886 - 2 - 2759 8180 hong kong office: unit no.705,level 7 tower 1,grand central plaza 138 shatin rural committee roa d,shatin,new territories,hong kong. tel: 852 - 2723 - 8086 fax: 852 - 2723 - 9179 technical support by email: sn8fae@sonix.com.tw

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